What’s Next In Advanced Packaging?

Experts at the Table: Semiconductor Engineering sat down to discuss 3D-IC progress and issues, photonics, and tradeoffs with different interposers and bridge technologies, with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What follows are excerpts of that discussion. To view part one of this discussion, click here.

L-R: Synopsys’ Roosendaal; ASE’s Chen; Amkor’s Kelly; Promex’s Otte.

SE: With 3D-ICs and 3.5D, thermal remains a huge issue. And it’s not just thermal. It’s thermal gradients, which can vary depending on the workload and the application. How do we deal with this? Is it going to hold up the rollout of full 3D-ICs, where you’re stacking logic on logic, or even memory on logic?

Kelly: We have to be able to combine thermal simulation and mechanical into so-called thermal-mechanical simulation. That’s a good start. The design tools are out there to be able to do that. It’s a lot more work. Everybody lives and dies by JEDEC reliability testing these days. You’ve got a high temperature, and you simulate a thermal condition at a high temperature and a low temperature. But that isn’t the same as looking at the real product and the temperature contours that exist inside the package. They’re extreme nowadays with a kilowatt part. We’re going to have to get better, and more pervasively use these thermal-mechanical methods to get a handle on this. It’s not just the die. It’s now the package, because everything’s linked together. That’s going to be critical, and it requires a global competence.

Chen: We have additional drivers to use tools to verify what we have, and maybe gain better understanding using different tools. Together with the model, we can go a step further on the inside with things like digital image correlation and 3D X-ray. At conferences, metrology also is being discussed in special sessions. People are rediscovering things they thought had gone away. Thermal-mechanical, thermal gradients, and stress are all related to each other.

Kelly: That’s a good point. If you don’t have good metrology, you can’t 100% validate all your simulation models. You need real-world measurements.

Chen: I lead the Heterogeneous Integration Roadmap, and we have been telling every technical working chair to look at AI and metrology. We need to plug these into our profession so the new graduates coming up will look at this and they will learn faster.

SE: So going back to 3D-ICs, is this going to happen? Are we going to have 3.5D where we can start isolating some of the logic on an interposer? Or has this stalled out?

Kelly: There are some 3D products out in the market already, putting chunks of SRAM on processors. Logic-on-logic is definitely on customers’ roadmaps, too, but it’s out there far enough that there’s a presumption we’re going to solve the thermal problems to make this possible. There’s also a presumption that through smart programming of the logic layer you’re not double-heating certain spots and creating hot spots that cannot be managed in software. Most of these solutions are still counting on a water-cooled jacket that is able to pull enough heat out of the bottom die to make it practical. At the university level, people are looking at cooling channels in the die, and those kinds of things that can be used at the very high end. But it doesn’t sound like a meat-and-potatoes solution for the rest of the market.

Chen: People are waiting for the first adopter. If there’s no problem, then everybody will jump in. Who wants to be the first adopter to say, ‘Let’s put a micro-channel at the back of my die?’ And even if you have that solution, it doesn’t apply when you have power in the backside.

SE: One of the challenges here is we’re not seeing the kind of industry learning that we saw in the past. There are a lot of one-off designs at the leading edge. How do we leverage that knowledge.

Chen: The chiplet ecosystem being developed by a lot of companies is going to push that forward. There is a lot of funding going into that ecosystem.

Kelly: That will have the effect of helping to standardize approaches, which will help to push everybody forward.

Chen: There is more information being developed and being shared. The number of papers going into the ECTC conference is increasing dramatically. That means a lot of people have done good research and want to put it on the table for everybody.

Kelly: I agree with that. There are some really good conferences. On the design side there is DesignCon and Hot Chips, and in the packaging world there are ECTC and IMAPS. Those are good sharing platforms. You can go there to explore and listen to what others have done and come away with some good ideas. Good ideas do proliferate, although maybe not as fast as we would like.

SE: In some of these new areas, like medical chips and optical, are you able to capitalize on what’s been done before?

Roosendaal: If I look at the designers who actually have to design the system, there are a lot of startups and small companies that basically start with one person who did a postdoc or PhD and had a brilliant idea but never designed a chip before. So that person would lead design software with guidance from the packaging and foundry side for how to do these things. And then there are people who have been designing analog or RF, and they have to do a photonic IC, so they will need to be guided on how you design a photonic circuit, and where you go with your routing and crossings and those kinds of things. But packaging seems not to be in the picture at the moment. They have an idea, and they start by trying to get to a functioning design.

Otte: There’s no question that we continue to learn. One of the things that goes on in our world is that somebody comes along and we work with them to develop a process. Typically, that requires a new tool, or at least a heavily modified tool, and that no becomes part of our repertoire that we have available for the future. We are continually adding to our repertoire through that mechanism. If nothing else, we as a commercial company tend to be driven by that. It’s the demand of our customers that causes us to buy new tools and to develop processes to achieve certain kinds of capabilities.

SE: Much of this is focused on power, right?

Otte: The trend is to reduce power everywhere. Optical technologies are an attractive way to do that, in concept. The problem with optical is it’s difficult to implement for reasons like tolerances and the fact that wavelengths vary so rapidly with temperature. We’re seeing people trying to control temperatures to a tenth of a degree Centigrade in order to control wavelengths. That’s really hard to do in devices that are dissipating watts of power. And so you get into a tradeoff. It’s kind of a bandwidth issue. How much wavelength variation can I tolerate here for the amount of power that I want to handle. It’s a nasty tradeoff, because the optical guys all want to stack 200 wavelengths in their optical fiber. And when you have that, things move around so much that it all gets confused.

Roosendaal: A lot of the designs are still single wavelengths, or maybe four to eight wavelengths, so single-mode. That makes things a little simpler. But in Europe, there are state-funded projects where, for example, you need to couple in at a slight angle. Otherwise, your light is going to be reflected right back into your laser, which is not good. So seven degrees was the angle, but there was confusion because the packaging house thought it was seven degrees in one direction, and the designer thought it was rotated. That’s a very simple mistake to make.

Otte: It’s the old mirror image problem.

Roosendaal: Yes, so you really need to agree on those very basic things. That includes temperature and the amount of light you lose if your coupling is not effective or misaligned.

SE: Swapping topics, where do organic interposers fit in these days? Warpage has been a big issue, but there seems to be a transition to smaller interposers aligned with metal. Is that progressing?

Kelly: Organic interposers are the low-hanging fruit, because in the OSAT world people have polyamide or similar dielectrics, and lots of coper platers. There’s an infrastructure for doing copper metal stacks. It’s a combination of reasonable cost, and you can get down to 2mm lines and spaces, and maybe even 1.5mm. But 2mm seems to be good for silicon, and it seems to be a sweet spot for most of the buses that have been looked at so far. It certainly has a great play when modules are reasonably sized. When modules get really large, and you’re taking defect density and applying it to an ever-larger module, yields get challenging. That’s where bridge technology looks a lot more attractive. Right now we’re very early in the whole giant transition going on here. The number of places that customers can go and get an RDL interposer solution is growing, and that’s good for the industry because you have sourcing flexibility and geopolitical diversity. It’s kind of, ‘Hey, it’s good enough and we can do it today.’ But it may not be the end-all in five years. The smaller parts will still make sense, but the larger parts will be doing something else.

Chen: I agree. We have been limited in terms of line spacing because of lithography. As we build better clean rooms and improve the lithography tools, we can go a bit more. It’s not just a question of lines and spaces, but how many layers we can have, what is the size, and how we can implement bridges into them. These are good technical development challenges. Personally, I believe there is a lot of room for advancement in materials, tools, and the way we design them.

Otte: In our world, we don’t see things down in the 1mm line and space. We seeing a lot 1 mil (25.4mm) and even down to 10mm, but not 1mm. From our perspective, that’s all being done at the university level.

Kelly: The die-to-die interfaces for chiplets, like UCIe or Bunch of Wires, normally require two to four layers of 2mm lines and spaces. Certainly, the silicon side can achieve much finer geometries, but nobody wants a really tiny cross section for signal integrity reasons. So 2mm has stuck for awhile, and it’s going to be around for a number of years. These buses are only 1 or 2 millimeters long. They’re super short. So 2mm is something most of the OSATs and foundries can build, and it’s a good place to be for sourcing assurance.

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