Why Inductance Is Good for Area, Power and Performance

By Magdy Abadir and Yehea Ismail

For chips designed at advanced technology nodes, interconnect is the dominant contributor towards delay, power consumption, and reliability.

Major interconnects such as clock trees, power distribution networks and wide buses play a significant role in chip failure mechanisms such as jitter, noise coupling, power distribution droops, and electro-migration. Buffers used in designing global interconnects to handle RC delay easily can contribute up to 60% of the total chip power. Therefore, robust interconnect design and modeling is critical for today’s leading-edge chips in order to meet performance and reliability targets.

Historically, the interconnect has been modeled as either capacitive or as an RC network. Designers have been ignoring interconnects’ magnetic effects, represented by inductance and inductive coupling. Instead, they have been using excessive margins and design methodologies to suppress the inductive effects. This has allowed them to continue to use existing chip analysis tools and methodologies, but at a significant cost in terms of chips’ power and performance.

For example, a designer may use differential switching on buses, where complementary signals are routed adjacent to each other. This effectively reduces the inductive coupling range and magnitude, because opposite currents close to each other produce opposite magnetic coupling fields that cancel each other out. However, it can consume four times more power and twice the delay compared to actively coupled wires with average switching.

Fundamentally, suppressing the inductive/magnetic effect can result in significant power and performance loss. While inductance is a reactive element that does not consume power, resistance is an active element that consumes power. In an interconnect network, inductance and resistance appear in series, so by suppressing inductance the resistive effect is amplified, resulting in greater power loss.

If managed appropriately, inductance can have positive effects, such as improving the signals’ switching time, reducing power consumption, and reducing the number of inserted buffers. For example, to drive long resistive interconnects and to reduce the total propagation delay, buffers are inserted based on an RC-only model that ignores inductance. This commonly used design methodology can result in much larger area because of all the buffers that are inserted. By using an RLC model, a better delay can be achieved with significantly fewer buffer areas, which also simplifies layout and routing. In addition, these buffers are large gates that consume significant portion of the total power, so considering the inductance effect can help lower power consumption.

With current design trends, such as 10GHz+ clock / 10Gbps+ data line speeds, lower noise margins, tighter integration of analog/RF and digital blocks, and decreasing feature sizes, inductive/magnetic effects are becoming too difficult to suppress and can no longer be avoided. Ignoring signal integrity and crosstalk issues due to inductive coupling also can result in undetected reliability problems.

Designing with an understanding of inductive/magnetic effects, rather than suppressing them, can result in chips with better performance, lower power consumption and smaller area. This requires robust tools that can accurately model and estimate the inductive/magnetic effects so that excessive over-designing, which comes at a significant cost can, be eliminated. The result is that leading-edge chips can meet performance, power and reliability targets.

—Yehea Ismail is the director of the Nanoelectronics and Devices Center at The American University at Cairo.