Find and resolve targeted physical verification issues during design and implementation, rather than waiting until signoff.
As every integrated circuit (IC) design company knows, the faster a design can progress from implementation to signoff verification, the better the chances are of meeting tapeout schedules. Meeting tapeout schedules improves a company’s chances of reaching their market targets. But as companies create larger and more complex ICs and move to advanced process nodes, the challenge of achieving that timely ramp to production gets hard. Like, really hard.
The electronic design automation (EDA) industry was literally invented to help design companies and foundries create and manufacture ICs faster. So it’s no surprise that EDA companies are once again stepping up with new solutions to help the semiconductor industry find better, faster ways to achieve successful tapeouts. Among the innovations are new tools and functionality intentionally designed to enable design companies to “shift left” to perform signoff-quality physical verification and design optimization earlier in the design flow. By finding and resolving targeted issues during design and implementation, rather than waiting until signoff, design teams gain significant productivity improvements while substantially reducing time to tapeout. How, you ask? Let’s take a look, using the Calibre nmPlatform toolsuite from Siemens EDA as our example.
Not every error is important during the design and implementation phases of the flow. In fact, quite a few of them are completely irrelevant—think about all the errors generated by missing or incomplete blocks. No design team in their right mind wants to run a full signoff verification at this stage, for that very reason. Wading through the results would be a nightmare.
On the other hand, there are certain systemic and critical errors that, if left to propagate throughout a full chip layout, will add hours, days, or even weeks to signoff verification time as each instance is debugged and corrected. By employing analysis-based techniques to pinpoint these types of errors, tools such as Calibre nmDRC Recon and Calibre nmLVS Recon can present a curated set of targeted design rule checking (DRC) and layout vs. schematic (LVS) checks that enable design teams to find and correct these critical errors in blocks and intellectual property (IP) during design and implementation. This selective set of checks can run quickly and efficiently. Innovative verification functionality, such as early short isolation, symmetry verification, gray-boxing of missing or incomplete components, and automated waiving of known false-positive errors, augments the selective checks to further reduce verification runtimes and eliminate errors that are irrelevant to early design-stage verification. Use of the foundry-preferred DRC/LVS tools ensures the design is Calibre correct, so design issues addressed early in implementation will not reoccur during signoff verification. Just like that, a design team eliminates the thousands or millions of errors that would be generated during signoff verification if those errors were allowed to propagate, or if they were fixed with a non-preferred solution that did not match the foundry-preferred reference tool. They also eliminate all the debug time and iterations that would be required to debug and correct those errors.
Of course, finding errors is one thing, fixing them is another. To help design teams get to root cause and correction faster, tools were augmented to provide better results visualization and automated root cause detection. Minimizing, grouping, and visualizing error results helps design teams efficiently and accurately identify critical and systemic design issues in early design stages. Presenting debugging information in intuitive, user-friendly formats can dramatically improve the efficiency of debug and help design teams take the most efficient path from dirty to clean designs.
To further enhance debugging, the toolset accounts for specific well-understood root cause identifiers. For example, identifying common design methodology mistakes that cause large numbers of violations, and automatically partitioning those errors into root cause categories, as well as identifying clusters of violations with suspicious feature commonalities that point to a common, but not yet identified, root cause, can help design teams sift through results more efficiently and analyze errors as groups, rather than randomly debugging individual errors without any particular strategy.
An effective shift left strategy doesn’t stop at DRC and LVS error fixing. Design for manufacturing (DFM) layout optimizations allow design teams to optimize a layout to improve performance and reduce the chances of manufacturing failures. Power, performance, and area (PPA) layout optimization has a significant influence on whether a design meets its intended power requirements, with key metrics for the P&R flow focused on design PPA goals. However, applying layout modifications during design implementation is typically difficult and/or time-consuming. The Calibre DesignEnhancer tool provides multiple automated layout modification use models that enable design teams to quickly implement analysis-based, correct-by-construction layout optimizations during IC design and implementation that improve power management and prepare designs for signoff verification. The use models currently available include:
Because the Calibre DesignEnhancer tool is built on the Calibre nmPlatform, it leverages foundry-preferred Calibre design rule decks, Calibre connectivity data, and industry-leading performance to improve both design team productivity and design quality.
In a shift left environment, Calibre verification is expanding into innovative areas of verification that were previously non-existent in industry design enablement flows. That expansion also means that people who do not traditionally use Calibre tools may be encountering them for the first time. With that in mind, the tools and functionalities were intentionally designed to provide automated, user-friendly, intelligent interfaces and processes that simplify, speed up, and optimize Calibre job configuration and invocation. This run optimization guidance allows design teams to maximize use of available resources and time, enabling them to better achieve their business objectives.
Whether designers are creating custom/analog or digital designs, the design implementation tool they are working in is not a Calibre tool. Calibre interfaces and use models enable designers to use Calibre tools and functionality within most design and implementation tools, enabling design companies to build a best-in-class solution using their preferred tools. The Calibre RealTime Custom and RealTime Digital tools provide designers with immediate DRC feedback in the design or implementation environment, using the same standard foundry-qualified Calibre rule decks used by Calibre signoff verification tools.
This integration extends to back-annotation of all changes applied to layouts during design and implementation. All layout modifications can be quickly and accurately back-annotated into the design database in DEF format. At the same time, an updated GDS/OASIS file can be generated to enable design teams to begin simulation or signoff verification runs.
Unlike signoff verification, implementing a shift left approach isn’t required. That puts the onus on EDA suppliers to deliver the performance and value that justifies a shift left adoption. But by freeing up design and implementation tools from functions they were never intended or designed to perform, and using tools designed from the ground up to provide targeted, relevant design verification and optimization, design companies can quickly realize the full benefit of implementing a shift left strategy.
Perhaps the best news is that shift left itself is an evolving process. New tools, techniques, and functionality are available to designers throughout the design and implementation flow to help them reduce the time and effort they need to complete their components, and more are coming. Machine learning (ML) and other artificial intelligence (AI) techniques are being used to help automate and refine design-stage layout analysis by identifying new and additional layout issues that are best addressed during design and implementation, as well as locate configurations of results across separate checks that can act as signals to help identify the optimal correction techniques. Intelligent resource forecasting also uses ML to support efficient resource use and provide the fastest turnaround times. Enabling shift left tools with the ability to run using onsite resources or the cloud provides companies with the flexibility to respond to business needs and changing priorities quickly and efficiently.
By understanding the purpose and intent of a shift left strategy, applying best practices for the use of shift left tools and processes, and taking advantage of platform performance optimizations to support new resource usage models, design teams can benefit from faster iteration times, significantly reduced manual review and debug times, and a reduction in the total number of signoff iterations required, resulting in increased productivity, higher quality designs, and faster time to market.
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