A long history and continued improvements are keeping 40nm processes relevant.
When selecting a foundry process for mobile consumer focused products, chip designers are considering the economics of the solution just as much as the technical specifications. Using the latest and greatest finFET process might get you performance headroom above your spec, but could cost significantly more than using a more established, proven process.
Today’s 40nm CMOS processes have been in volume production well over five years and deliver consistent performance and yield. The performance is sufficient for all but the most demanding consumer applications at power levels that won’t break your power budget. Because it is a mature process with proven defect density and yields, the cost for a given die size is considerably lower compared to newer, more advanced processes, and multiple 300mm fab locations with geographic diversity ensures that there will be capacity to support the highest volume consumer market application demands.
In particular, the combination of performance, low power, and value benefits the mobile consumer application segment.
“UMC is pleased that our customers have been able to achieve such excellent results using our industry-standard 40LP process,” said S.C. Chien, senior vice president of Corporate Marketing at UMC. “The low power capability of UMC’s 40LP technology combined with our ability to customize the process and our ability to deliver high wafer volumes from multiple fab locations have allowed us to help our customers excel in consumer applications.”
UMC has made process optimizations to their 40nm low power process that allow it to deliver outstanding performance at industry-leading low power levels. This combination of low power together with high performance make it an ideal solution for today’s demanding consumer device manufacturers such as Lattice Semiconductor.
“Lattice designed the architecture of the iCE40 Ultra family to be optimized for low power consumer applications,” said Rick White, corporate vice president, operations at Lattice Semiconductor. “UMC optimized their 40nm low power process to meet our power targets, and their expanding 40nm capacity at multiple locations allows us to meet consumer demand.”
UMC has been expanding its 40nm process 300mm wafer capacity with production in Taiwan and Singapore today, and has just started high-yield, volume production in mainland China. This capacity ensures that customers such as Lattice Semiconductor can get the wafers they need to be able to ship the volume of parts needed to meet the needs of their consumer market end customers. UMC also has an ultra-low power version called 40ULP that further reduces active and standby power to enhance battery life in portable devices.