Addressing Test Time Challenges

Improving test strategies is key to cutting costs.


Unit test time on automated test equipment (ATE) is one of the major components that affects the total cost of manufacturing for semiconductor suppliers. The test programs for each unit can be comprised of thousands of parametric and functional tests that are performed to screen out defective units or dies. However, tester time is expensive, so suppliers are always looking for ways to reduce the test time per unit by exploring multiple options:

1. Eliminate redundant tests;
2. Re-ordering of tests (arrange the test flow to screen out the major failures early in the flow), and
3. Sample testing of “always passing” tests, or potentially even removing them.

With good device knowledge, product and test engineers can remove many of the redundant tests. And with a basic understanding of the test flow, engineers can also re-order the test flows to arrange the frequently failing tests to be run in the front in the flow so that overall test time is reduced.

For option 3, this is where the test engineers need to collect all the pass/fail data on all the units to make intelligent choices about how to do sample testing. Engineers typically institute sample testing, or remove tests that always pass, by doing test code modifications. In many cases, test program code is not easily modified and might require complex revisions, which can lead to multiple iterations of the test program. In addition to increased development/debug time for any program modifications, the effort to implement new test programs across all manufacturing sites can be a long and costly process.

To help semiconductor manufacturers address these challenges, Optimal+ provides an Adaptive TTR solution that analyzes and implements intelligent test time reduction while maintaining product quality across a company’s entire semiconductor supply chain.

Figure 1 below describes how users can select all the tests under consideration for TTR. Figure 2 shows the TTR options that can be selected by the user including: the sample rate, tests sampling options, site specific options and whether to do parametric TTR or P/F (pass/fail) TTR.

Figure 1

Figure 2

After the TTR simulation is run, the application then provides a Pareto report (see Figure 3) on what the potential test savings would be for every selected test in the test program. Using the Pareto table combined with the test engineer’s product knowledge, the user can select the set of parametric and functional tests that they believe will yield the best TTR results. At this point, the user can now run a TTR simulation analysis on historical data based on the selected tests to calculate the cost savings without any quality impact for the product under consideration.

Figure 3

Once the users are satisfied with the historical simulation results, they can further verify the TTR on a live set of units, before deploying to their entire manufacturing flow. This verification will differ from customer to customer based on volume and may require further refinement to the selected set of tests. Once verified and implemented on a given product, the application adaptively performs the sample and full testing. Intelligent algorithms within the application can also track statistical trend data for parametric values to dynamically adjust or stop sampling based on user-defined upper and lower estimating limits. This requires no test program code changes.

Figure 4 shows the initial full chip test results, followed by the sample test mode when instituted. During the initial full chip testing, the initial volume of product is 100% tested and then a sample mode is adopted. During the sample mode, full testing is based on the frequency selected by the user. Figure 5 shows the results of the sampling TTR on multiple lots of a product. The savings show a range of test time savings from 15% to 24% on a lot-to-lot basis (note: The Y-axis does not start at zero).

Figure 4

Figure 5

Many customers have applied Adaptive TTR on high-volume devices and have seen anywhere from 10% to 50% test time reduction with no impact on product quality, significantly reducing overall manufacturing costs and simultaneously increasing product throughput. To learn more about the Optimal+ Adaptive TTR solution for your semiconductor products, please contact your Optimal+ by clicking here.