Back To Basics On Multi-Voltage Verification

In the new world of multi-voltage chips, design analysis concepts need to be rethought.

popularity

It has been more than a decade since the paradigm of voltage-aware Booleans came about and the world of multi-voltage verification took off. We started with 3-5 island SoCs and now stare at 300+ islands on a single SoC. While we have a well-developed standard (IEEE 1801/UPF) for the expression and analysis of voltage variation, it is apt to not forget some of the basics and see how they will carry forward into the IoT era.

First things first: what is the definition of multi-voltage? In the strictest of terms, it is a phenomenon where there is a voltage difference on a spatial or temporal aspect of a design. IC designs have always been multi-voltage designs – however, hardware description languages abstracted away voltage into a universal, always available entity and wiped out any level differences between spatial elements. Hence, the notion of voltage as a basis for logic levels and conversion exited the RTL world.

The advent of modern power-managed designs that aggressively implemented power gating, DVFS, retention, etc. changed all that. We needed the voltage entities back in the hardware description in a manner that was consistent across all phases of the design cycle. Initially many proprietary formats abounded, but we eventually converged on a single IEEE standard, the 1801/UPF description of multi-voltage design and behavior.

The trouble is that a lot of design analysis needs to be “unlearnt” and adapted to the world of multi-voltage. Concepts such as isolation and level shifting need to be understood not just from a logical perspective but also an electrical perspective; here comes the first ground principle (forgive the pun) – our notion of logic levels is a representation of electrical levels to which nodes are charged. Hence, a “1” on a waveform really needs to be annotated with respect to its source voltage. It is in this context that I had created a simple mnemonic – Domain is the Drain of the Driver (and may the purists of CMOS forgive me for this poetic liberty). This simple mnemonic was a reminder to design engineers that logic levels needed to be constantly traced back to the voltage levels of their driving elements.

The reference to the driver is more than symbolic. Spatially, it helped create a basis for representing the transfer functions of CMOS in spatial crossings and create rules for static and dynamic analysis around them. Temporally, it provided a basis for distinguishing between the multiple on levels, off values and standby/partially on levels for the CMOS logic. We could even distinguish between combinatorial and sequential cells in terms of their “off-on” behavior.

All the changes brought about by multi-voltage representation were hence quite problematic for design and verification engineers to adapt. Familiar debug patterns, messages and checkers broke. Assertions became invalid and new ones were needed. Bug patterns that were purely logical and transactional added control and electrical signatures. Coverage metrics needed to be redefined too.

We now face one more increase in complexity: designs have become SoCs with hundreds of islands and hence, a gigantic mass of complications like the ones described earlier. In addition, most SoC activity is software driven, necessitating a translation between software activity and electrical behavior. Thankfully, the advent of finFET technology has not brought about a fundamental shift in CMOS behavioral abstraction, so we just need to create the handles on size and software. On the other hand, the advent of dark silicon underscores the need (and urgency) to handle complex designs.

The burning question is how we will adapt to software-managed SoCs with hundreds of islands. Whatever methodology we adopt, one thing is clear: we have to keep going back to the basics of how logic analysis correlates to control of voltage. The electrical nature of multi-voltage can never be forgotten when it comes to accurately analyzing designs. As we scale the application of modern SoCs into areas such as IoT, medical devices, automotive electronics, etc., this back-to-basics principle will keep us going.