Lots of choices and requirements make this task harder than it might appear.
By Bhanu Kapoor
The design and selection of an SoC power delivery network (PDN) presents unique challenges, and its design is critical to achieving power consumption goals of the design. This is true when your PDN is external and based on off-the-shelf components as well as when it is being designed on-chip as part of the SoC. This article explores the external situation.
Power architecture of a given power-managed design determines various power modes of that design. Each power mode implies a set of power supply voltages and load current requirements for the PDN. These requirements drive the selection of voltage regulator modules (VRM) that supply the design with appropriate voltage and current levels in different power modes of the design. This process is a lot more challenging than it appears to be.
To begin with, you have the task of establishing target impedances to be met across a range of frequency values for the PDN and then designing in the appropriate decoupling capacitors to meet impedance goals. This is a challenging process in itself, but it addresses only part of the problem. The selection of appropriate VRMs to supply the design can be equally challenging. Here are some of the factors:
All of these requirements, as well as a large number of choices, make this task a challenging one. And it can get more complex if you bring variable voltages into the picture. It is critical that PDN is done right because an efficient PDN saves a lot of effort in optimizing power of the design. It also gives you a clear edge in time-to-market with a low-power device.
–Bhanu Kapoor is the founder of Mimasic, a consultancy specializing in low power and verification.
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