Things to watch out for and other considerations when moving to the next process nodes.
FinFET devices were developed to address the need for improved gate control to suppress leakage current (IOFF); DIBL (drain-induced barrier lowering); and process‐induced variability below 32-nanometer. FinFET technology is now in volume production.
To fully realize the advantages of FinFET devices, physical IP must follow the same trajectory that has benefited digital design. That includes: 1) device scaling; 2) lower power consumption; and, 3) higher speeds. To achieve this, analog/mixed-signal development techniques and design styles for foundation (standard cell libraries and embedded memories) and complex (USB, DDR, PCI Express) physical IP have to be re-created and implemented with very close foundry cooperation.
From a designer’s perspective whether the technology is planar or FinFET, the parameters of interest are the same—transistor gain, output conductance, transition frequency, matching, noise and device aging. Their target is to achieve performance while meeting the system-on-chip (SoC) constraints of power and area. In terms of new analog/mixed-signal design styles, FinFETs provide an improved sub-threshold and short-channel behavior, associated with low leakage currents; very low output conductance due to the lower channel doping, providing an advantage in terms of instrinsic gain; better matching behavior; and the metal gates eliminate poly depletion effects. For SRAMs, the higher gate capacitance means that the fan-out needs to be adjusted, i.e., the lack of body effect requires that the transistors are adjusted in series for pull-up and pull-down. Although not strictly related to FinFETs, high-k dielectrics can be used to reduce gate tunneling currents, but this increases flicker noise or reduces mobility. An interesting aspect to this is that designers will leverage FinFET properties to invent new circuits in the future.
This article highlights the FinFET transistor characteristics that make them different for physical IP design compared to planar devices, the impact FinFETs have on existing circuit designs, and layout topologies for DDR, USB, PCI Express and foundation IP.
Lower leakage in FinFET devices is achieved by the lower DIBL and a lower sub-threshold slope. The DIBL effect appears as the source and drain get closer. They become electrostatically coupled, so that the drain bias can affect the potential barrier to carrier flow at the source junction, resulting in subthreshold current increase. In the subthreshold region, the channel surface potential is almost constant across the channel and the current flow is determined by diffusion of minority carriers due to a lateral concentration gradient. In this region, the drain current depends exponentially on the gate-source voltage. Because of the lower channel doping, the threshold variability is much better controlled and there is less variability caused by random dopant fluctuations. The lower operating voltage of FinFET devices results in up to 50% dynamic power savings. The advantages can be summarized as better technology parameters that give lower leakage and dynamic power consimption. Figure 1 illustrates the voltage and current waveforms being impacted by the number of fins delpoyed on one transistor. In planar technologies this was done by changing the width of the device.
Some additional factors need to be considered when implementing FinFETs for physical IP design. Quantized widths and channel lengths will completely change the development style for full custom design. Body biasing is totally ineffective, as the body effect is the change in the threshold voltage of the transistor because of the non-zero bias to the body. This technique has been used for many technology generations to reduce channel subthreshold leakage. Because fins are fully depleted, there is very little body effect (Vt dependency on substrate bias).
The multiple fins making up FinFET transistors introduce a large number of new parasitic resistance and capacitances to be considered, modeled and extracted from FinFET-based designs. Figure 2 shows some of the parasitics introduced by this technology.
Potential self-heating issues may occur because of the physical isolation of the FinFET, especially when used in circuits with a heavy-duty cycle such as clocks. Self-heating is a function of the number of fins and the number of active lines per transistor. Through optimization of the gate stack with appropriate oxide scaling and metal gate work function tuning and so on, reliability similar to planar can be achieved.
Self-heating shows negligible impact on circuits where bias points are set sufficiently high above the threshold voltage, but may be an issue on FD-SOI processes. Thermal aspects of ESD can also be an issue.
Another consideration is device aging. Degradation and aging due to negative bias thermal instability (NBTI) can be worse than planar, but plans to bring it back in line with planar are under consideration at all foundries.
The good news is that FinFET SRAMs have higher performance and lower leakage than planar equivalents, and can operate at lower operating voltages. The devices offer good static noise margins at these low voltages because dopant-based variability is low, and it’s possible to achieve good noise to signal ratios. Read and write margins are smaller, and their distribution narrower, because of the lower operating voltage. Good static noise margin can be achieved at the lower supply voltage, decent noise to signal ratio can be achieved (with a β=2 for example) and the read margin/write margin distribution is narrower than in planar.
Challenges for SRAM designers working with FinFET processes include the fact that the beta ratio is a quantized number; thus, fine-tuning beta is not possible. The narrower static noise margins resulting from quantized beta and lower VDD operation pose challenges for both the read and write margins, so designers need to add assist circuitry to ensure reliable operation. Body biasing doesn’t work, so new ways to control leakage must be developed. And self heating may be a problem, because fins are less efficiently cooled. Realizing long channel devices requires a lithography-driven double patterning versus spacer approach, and has limited options. Stacking short channel devices in series, the multi-fin pitch and layout effects on devices are critical. Consider, for example, the lonely FinFET phenomena.
As processes become denser, the channel area will decrease and threshold voltage variability will increase, challenging SRAM designers. The resistance and capacitance of the source and drain regions also present a hurdle to good FinFET SRAM performance. And those who are trying to develop such IP need mature device models that capture FinFET effects associated with new surface orientation, surface scattering, ballistic transport, corner effects, and more.
For complex physical IP blocks such as USB, PCI Express and DDR, the architecture and schematics can change considerably compared to the planar versions. First, the PMOS and NMOS have similar drive strengths. Device matching is better than planar, although variation of the gate oxide, permittivity and the work function along the fin height can vary. The aspect ratio (width and length) is mapped to the FinFET gate length and number of fins. There is strict binning of device sizes, meaning that custom device sizes and layouts are not possible. Basically, the quantized devices lead to stacked devices in the architectures and this increases parasitics, requiring new designs for high-speed blocks used in DDR4/LPDDR4 running at 3200 Mb/s and PCI Express 4.0. As with memory design, aging simulation is important, NBTI dominates PBTI.
In terms of layout design for these complex physical IP blocks, additional considerations need to be taken into account:
The lower power supply voltage impacts voltage headroom (dynamic range) and PSRR (power supply rejection ratio) of key circuits, moving toward more voltage regulation to avoid low supply corner performance issues. Despite the lower I/O voltage, the system specifications remain constant—for example, the output swing in a PCI Express transmitter or the 5V tolerance requirements for USB. These high-voltage tolerance requirements can be a major concern in FinFET technologies due to reduced breakdown voltages, and usage of deep nwell for 3.3V I/O may be needed. The increased capacitor density helps by getting more efficient decap in the same area. Due to more sophisticated power modes and power-aware settings in the .lib (timing) files, power gating on circuits is being used. For latch-up, substrate contacts need to grounded and ESD checks must be developed. Finally, the compute power requirements are much higher (device/interconnectivity is more complex).
This article described the impact of FinFET technology on lowering physical IP power consumption. In order to achieve this, many additional factors need to considered that fundamentally change the design styles of the engineering team. To get performance while meeting the SoC constraints of power and area, designers still need to care about the same parameters (gm, gd, Ft, Fmax, matching, noise) in planar or FinFET. What’s different for planar technology is that process information must be included to create optimized FinFET schematics, layout and metallization starts earlier in the design process and new design styles, EDA tools implemented in-house are needed to meet IP specs.
FinFETs provide improvements in device matching, lower device variability, and better leakage and dynamic power. But quantization, high-voltage tolerance and increased parastics require new circuit architectures to meet power, performance and area in advanced SoCs.