With so many unknowns about future designs, it’s hard to figure out where to place bets.
EDA and IP suppliers are engaging with foundries earlier with each manufacturing process node, while those foundries are providing ever more optimized and tuned processes to their customers. As part of this, IP providers must port their IP offerings to the various foundries and processes, putting a squeeze on resources.
That raises some difficult questions, such as how to prioritize their limited resources and how to stay nimble in a fast changing environment. Complicating matters is the fact that no one is quite sure what IP will even work in the future because some of these end market, such as IoT and connected everything, are new and evolving.
“When you look at what’s happening in compute at the edge, that’s all about specialized applications,” said Zach Shelby, vice president of IoT marketing at ARM. “It’s about being able to process data in the right way for the kind of compute load that we have. We’re seeing a huge change in the type of SoCs people are doing. FPGAs are one aspect of this. When we get into specialized compute loads, we’re seeing SoCs designed just for those applications. These are very high speed cores with very high power efficiency. But I’m more concerned about the edge problem. What we find to work in algorithms for gaming are all deep learning applications. These are not traditional network-based applications, so we’re falling behind in computing. That’s an interesting challenge. The new chips that were announced at IEDM were all neural network chips. You’re doing deep learning, but over traditional networks. That doesn’t help us. FPGA doesn’t help us if it’s not power-efficient. How are we going to do deep learning at the edge?”
Further, EDA venture capitalist and advisor Jim Hogan noted that a programmable fabric can be used, but not at the edge. He also believes neural nets are interesting. “You want to direct the search in an interesting way. It’s likely a microcontroller. You use those for specific applications. They’re going to be application-specific edge devices.”
Admittedly, those challenges are still a little bit out on the horizon. For now, prioritizing investments for IP development is a looming challenge. John Koeter, vice president of marketing for IP and prototyping at Synopsys, said more falls to the IP providers, and it’s a challenge to make sure they are addressing what the customers need.
Moreover, he said the foundries are highly specializing their processes for individual market segments as well as for competitive reasons, and they are turning out many, many different process variants. “From an IP perspective it’s a significant challenge because as the fabs keep providing optimized and tuned processes for their customers, we have to port our IP to the various different foundries and make some prioritization decisions of where we want to invest. It’s an ongoing challenge for an IP company.”
Porting a piece of IP or an IP subsystem from one foundry process to another is no small task. It takes time and money.
“There’s an additional dimension of complexity, which is the fact that as we collaborate more with our customers we are engaging far earlier,” Koeter said. “The last three or four years, we’ve been engaging with [version] 0.1 process design kits, and even in some cases 0.01 process design kits. It definitely creates a burden on us in terms of additional engineering resources. Through these collaboration business models that we have with our customers, we work with them to look at the various business structures. But in my opinion, the business models in the IP industry definitely need to evolve to take into account this increasing turn in the number of processes in this early collaboration. That’s something that as an industry we’re just slowly starting to come to grips with. It’s something that we collectively, with our customers, need to put a little bit more thought into—how we defray the increased costs that we have in those areas. Everybody gets what they need when they need it with a fair return on investment.”
Of course, to truly enable the IP development, the foundries themselves must provide certain technical details to the EDA and IP providers, reminded Mike Gianfagna, VP of marketing at eSilicon. “If you go back not too long — even just a few years ago — the foundries were the Fort Knox, they were the NSA headquarters and it was very hard to get any information out of them at all. They were very stingy with the information and as an EDA vendor you were guessing more often than not.”
But that has changed, Gianfagna said. “Foundries are more collaborative, more open. The folks that need to know are getting pretty high-quality information. Now, the foundries still aren’t going to disclose their yield equations or the details of the process, but you actually don’t need that information to build accurate models and to build IP. So there has been an improvement in collaboration here and it is good business on both sides, because the foundries have realized that without an ecosystem the process isn’t as valuable. Similarly, if you have a new semiconductor process that is just absolutely stunning and ultra-low power and ultra-low feature size and there is no EDA or IP support for it, who cares? The people who could build their own IP on their own infrastructure — there are only a few of those — have a staff of people. If you looked at the org chart for those companies, you might come to the conclusion that they own a fab because they have process engineers and all kinds of people but they can afford to do that. But that’s the rarefied air at the top of the pyramid who can do that. Everybody else has to rely on the ecosystem.”
As for how IP providers decide what to focus on, he said there are two answers. “When faced with this situation, one of the first things that we do is the standard market analysis. We look at the markets we support and what the technology demands are, what people are extrapolating in terms of power and performance, and then we will pattern match that to the processes and say, based on our market research, this is where this market is going. So we had better produce memories or I/Os that are in this power and performance range if we want to follow that to market. That will be part of how we decide where to invest.”
That’s on the traditional front, but there is another piece to the ecosystem today, which is the strong role of the foundry, Gianfagna explained. “We talk to the foundries and oftentimes they will help us make the decision. TSMC says, ‘I’ve got a new 28nm flavor that’s going to be focused on this market and I am going to promote it to that market. I am missing high-performance memory for that market and you, eSilicon, are doing high-performance memory. I want you to build memory for this process target. And by the way, here’s a couple of free multiproject wafer runs to validate and silicon-harden your IP.’ It’s hard to say no to that. It is hard to say no for two reasons. Of course they are offering us this free stuff which is always nice, but that’s actually not the main driver. The main driver is if a foundry is saying that they are going to make a market out of a process and they are going to put effort behind it to make it real, that’s a perfectly fine thing to follow. We trust them and we believe they are going to do it, so we want to be on that train.”
In addition to this, a number of IP providers point to the usefulness of the foundry roadmaps, where they are putting effort, where they are doubling down. The foundry symposiums and meetings are critical to learn about foundry direction, as well.
To this end, Navraj Nandra, senior director of marketing for DesignWare analog and mixed-signal IP in the Solutions Group at Synopsys, noted that all the foundries have roadmaps today that are going toward finFET technology. Some are already in volume production. “TSMC and some of the other foundries are looking at new applications like automotive, and that requires a whole set of different qualification standards. So you’re starting to see foundries now talk about the ability to support some kind of automotive quality requirement, be it associated with functional safety or extended temperature ranges. There is also lots and lots of talk about what process technologies are needed for the IoT. These are specifically targeting very low leakage technology, so we are seeing foundries coming up with things like a 55nm and a 40nm, or even 90nm embedded flash technology with ultra-low power.”
The availability of process notes and the availability at certain foundries now is a big consideration, Nandra said. “There are more choices than before in terms of where you can tape out your chips. How that impacts EDA and IP companies is interesting because if you really had the resources to be able to do it, you would want to be able to have IP and EDA for all of the different flavors and for all of the different foundries. You want to be able to service all of that, but there is obviously a resource constraint. Once you have that, then you start to look at your best ROI and typically you would go for the one that has the highest adoption in the fabless ecosystem. Clearly today that is TSMC.”
That’s where a lot of semiconductor and systems companies developing chips put their priorities initially, but things are getting very colorful as far as process options go. For instance, Synopsys’ IP portfolio supports essentially all the major foundries, Nandra said.
And interestingly, he noted that when showing customers the roadmaps for the analog and mixed-signal IPs, which are foundry dependent, there are almost 100 pages of different IPs that Synopsys is supporting at all the different foundries on all the different process nodes. “We have tried to keep very impartial in terms of letting customers continue with their choices with different foundry options, so for us we treat each foundry as an equal partner. Of course it is a very competitive landscape, so what sometimes happens is that foundries will try to accelerate the roadmap in terms of IP availability and they are willing to fund the IP development [among various IP providers] to enable the ramp up of their technology. From their perspective it makes their node more attractive to customers.”
Change is coming
Looking ahead, the way that the foundries interact with the ecosystem is changing.
Gianfagna sees a bimodal dynamic at play. “There is still the tip of the iceberg gargantuan customers that everybody chases, and that does drive a lot of the business up, and drive a lot of the consumption at the major fabs. But that’s not the whole story. Call it whatever you want: IoT, IoE — it is the coming massive interconnectedness of all kinds of devices — and you need silicon for all those things. So there is another growth path for the semiconductor industry that is going to fundamentally change the business, and fundamentally change the way the foundries interact with the end customer.”
At the top of the pyramid are the exceptionally-educated consumers who know exactly how to build a chip, he said. They know exactly what they want, and can ask the probing, detailed questions to get exactly what they need from the foundry.
“When you look at this other market, what you have is massive numbers of people building products,” Gianfagna noted. “Some will fail, some will succeed, but these are system people. They know how to build a system, they know they need a chip, they know the chip is a necessary evil, but they really don’t know how to build the chip or may not even know what is inside the chip. They just know they need a device that runs at a certain performance. It has a certain cost performance at a certain power, and they desperately need someone to shepherd them through the process where they go from their system concept to a delivered piece of silicon. There is an intermediation opportunity there that is very real and very significant, where you’re going to need a way to find IP, a growing and exploding amount of semiconductor IP, a lot of sensors, a lot of low-end processing capability, all kinds of ultra-low power, networking and wireless interfaces. You need all of that IP and you need a way to translate your system requirements into collections of that IP that will hit a very specific power performance and area curve, and to be able to do that in a highly automated efficient and predictable way. And it is on older technology nodes too—55nm, 45nm, 60nm, 65nm but with some very new and cutting edge design styles applied to them with a very new and different kinds of IP.”
Those who can figure out how to deliver on that will likely do well because the foundries no longer can deal with just with one or two gargantuan companies. They’re going to have to deal with some kind of outlet that can address that massive and growing market of system companies.
“In this way the semiconductor industry will go through another rebirth, sort of like what happened in the early ’80s when the ASIC was born and companies like LSI Logic and VLSI Technology came onto the scene. That made custom chips available to the common man. It used to be you could only get a custom chip if you were rich enough to own everything. Now you could build a custom chip with LSI logic. There was a rulebook and you could use their design center and you didn’t have to own everything – in fact you didn’t have to own anything and they would help you through the process,” Gianfagna recalled.
Of course chips became more complicated and more sophisticated and the industry has swung back to the elite kind of model, where the ultra-rich and ultra-smart build the super custom chips.
However, the pendulum has begun to swing the other way. “The old customer was someone who knew how to build a chip but just couldn’t afford it, and needed a cheaper way. This new customer is going to need a chip, they’re not going to be rich in cash, but they’re not going to have the chip design skills either, so it becomes another level of sophistication to deal with a customer,” he concluded.
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