New physical synthesis technologies can help mitigate IP development risks.
By Sudhakar Jilla and Arvind Narayanan
The use of IP (intellectual property) as basic building blocks is an established practice for SoC designs. Most IP is developed without chip-level context and very little knowledge about physical design, which can introduce unwanted schedule risk into the design process. Much of the risk of IP development can be mitigated by using new physical synthesis technologies to qualify and validate IP blocks before handoff to the physical design teams. Figure 1 illustrates the difference between a traditional flow, which could lead to more iterations, and a next-generation flow that incorporates synthesis, floorplanning, and optimization during RTL synthesis.
Figure 1: Integrated RTL-level signoff flow.
There are many advantages to pulling IP development and validation early in the design stage, including fewer iterations between IP development and physical design teams, better quality IP, and reliable project schedules. For example, a backend design team could get an IP only to discover timing and congestion issues during physical floorplanning. There is no easy way for the designers to tell which part of the RTL needs to be fixed because there is no direct link between the IP RTL and the physical placement that allows designers to pinpoint the problem. If the IP developers could generate floorplans and perform early analysis of the IP as part of the synthesis flow, they could deliver highly-implementable IP to the physical implementation team.
Having the ability to determine the feasibility of the IP implementation with early analysis during RTL synthesis enables IP designers to deliver IPs that are free from timing and congestion issues and can be implemented across multiple floorplan configurations (square/rectangular/rectilinear). Newer physical RTL synthesis tools are able to integrate synthesis, floorplanning, and optimization early in the RTL synthesis stage that enables IP designers to perform IP prototyping and qualification.
The new physical RTL synthesis tools can create a floorplan at the RTL stage by pulling placement along with synthesis. The physical placement information is used early in the design flow for accurate timing and congestion analysis. Once the initial floorplan is created, congestion, timing, power and area metrics can be analyzed to make incremental changes to fine tune the floorplan. It is this ability to floorplan during RTL synthesis that enables better IP development and qualification. Early analysis of performance, power, and area plus timing and congestion gives the IP designers confidence about the feasibility and quality of the IP implementation. Performing IP qualification with RTL floorplanning, as shown in Figure 2, enables quick iterations at the RTL level and represents a huge reduction of risk and uncertainty in SoC projects.
Figure 2: Next-generation IP qualification flow.
Another useful capability for IP designers is to be able to visualize the full placement of the design along with the timing paths and RTL source code, which allows for quick debug. A cross-probing interface is shown in Figure 3. Instead of going through multiple frontend–to–backend iterations to identify timing issues and congestion hotspots with the IP, the designer could trace and fix the problems before handing the IP off for implementation.
Figure 3: Cross probing to identify timing bottlenecks.
A next-generation RTL IP qualification and floorplanning flow lets RTL designers create and validate physically implementable RTL IP without having to depend on iterations with backend designers. The result is reduced iterations, reduced risk to schedule and improved IP quality.
For more details about performing fast IP qualification during RTL synthesis, download the whitepaper IP Qualification with Oasys-RTL.
Arvind Narayanan is the product marketing manager, IC Implementation Division, Mentor Graphics.