Power Management Validation

How to obtain a realistic power profile for an SoC.

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Power consumption is becoming a critical aspect of hardware design. No longer is verifying an SoC solely answering the question “does it work?” Now designers must also answer the question “does it meet my power budget?” When trying to find power issues it is critical to run the complete system in a realistic manner—at the system-level when the design/verification team is looking at the effects of power during HW/SW validation. Only when full software loads are running and the caches are in a typical state can one get a realistic power profile.

As this paper shows using a real-world design, Veloce emulation gives developers the needed performance to run algorithms to the point where a problem can be reproduced. Codelink delivers the debug visibility needed to discover the cause of the problem. And an activity plot captures the relative power consumption of a design. Together these give engineers the information and the means to make higher performing, more efficient designs.

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