Why deep sequential analysis is so valuable.
Resets initialize hardware by forcing it into a known state, either on design start up or to recover from an error. In today’s SoC designs, it is not uncommon to see designs with millions of registers that have resets. Unfortunately, many of these resets are redundant. Leaving these unnecessary register resets in the design leads to increased power consumption, excess area, and routing congestion. Figuring out which registers do not actually require resets is extremely challenging. Traditionally, designers use manual techniques to identify redundant registers. But what is really required is an automated approach.
Power-efficient design is one of the primary design goals today. Registers with resets require larger technology cells, which in turn increases the area and power consumption of the design. Compare the simple example of a register, with and without reset capability:
Adding preset and clear requires 3-input NAND gates that add significant area and power consumption to the register. Now, multiply that by a million, and it can be seen how resets affect the power and area statistics of the design. Therefore, for low-power design, there is significant motivation to find and eliminate redundant resets.
A common method to detect redundant resets is to use simulation to:
However, this technique requires multiple permutations of the registers and it is very time-consuming. Another approach is to employ X-propagation:
In the X-propagation technique, registers without resets are in the uninitialized state X. The designer uses simulation to evaluate whether an X can reach primary outputs. If the X cannot reach the outputs, the reset is redundant. However, this technique suffers from long runtimes and it is not practical for SoCs that contain millions of registers.
A key technology for automated techniques is deep sequential analysis, found in Mentor’s PowerPro RTL Low-Power Platform. This multi-cycle analysis of the RTL design examines the logical relationship of the registers in order to generate all the possible enable conditions. Then, the analysis trades off area, timing, and power to find the optimal enable condition.
The key to detecting redundant resets is observability. In particular, the tool forms observability don’t care (ODC) expressions that define conditions under which the reset signal’s value has no impact on the design’s primary outputs. This means that the reset signal is never observable. The ODC expression must be analyzed by the tool in order to determine if it is “safe” to remove the register reset. For example, if we have a simple circuit where two registers drive a MUX via combinational logic and the select signal of the MUX is controlled by a register, the tool must evaluate the safe ODC expressions in order to determine if any of the resets are redundant:
In this example, the safe ODC expressions for the G1 and F1 registers are:
SafeODC(G1) = (S1 == 1) SafeODC(F1) = (S1 == 0)
The tool applies the reset values for register S1. For the G1 register, the ODC expression evaluates to always false: SafeODC(G1) = (0 == 1), so the reset is not redundant. For register F1, the ODC expression results in a tautology: SafeODC(F1) = (0 == 0), so the reset is redundant and it can be removed.
Then, the original RTL can be modified to account for the redundant reset for register F1 by removing the reset and non-reset assignments and inserting an always statement that does not contain the rst signal in the sensitivity list:
In summary, the tool performs a set of activities in order to identify redundant registers at the RTL in order to generate optimized code:
In order to measure the effectiveness of automating redundant reset elimination, many large designs were analyzed and the power and area impact was measured. For example, in six real designs, the percentage of registers that contain redundant registers (Reset Load Reduction) varied from 10% to 72%:
Additional tests on these designs showed that redundant reset removal can reduce area by up to 3%. By examining the tool reports, analysis showed reduction in sequential power up to 22%. Additional post-layout metrics were collected to measure utilization, buffer count, wire length, and the number of vias and the results were significant:
By employing a novel algorithm that uses observability-based sequential analysis for redundant reset elimination, designers can reduce sequential power consumption and area, and improve the layout of the design to minimize routing congestion.
To learn more about eliminating redundant resets, view the On-Demand Web Seminar.