UPF 3.0 means IP vendors no longer have to provide 57 varieties of power models.
The increased levels of interest we have seen over the last couple of years in system-level power modeling and energy-aware system-level design methodology, coupled with broad participation in the associated industry standard activities around system level power, gives us a clear indication that a shift in focus for low-power design is taking place. Our attempts to deliver energy-efficient high-performance systems now demand that we take a more holistic view of power mitigation with a system perspective, that we address thermal design issues and deal with power and performance duality concurrently across both hardware and software.
Long gone are the days when we could expect to deliver energy efficient systems by simply tuning IP power consumption during physical implementation. The complexity of platforms today demands that energy efficiency be architected and designed into systems, and that includes the hardware component the software component and the system power management component. The robust tools and design methodologies that we have in place today make the low power physical implementation (RTL to GDSII) of a piece of IP fairly straightforward and so low-power system design is now the primary area of concern. Taking a system view of low-power design has considerable and obvious advantages over the more traditional IP-centric approach and provides us with the greatest opportunity for energy savings.
We know that the way in which a platform is used absolutely determines its energy consumption, and so scenario-driven energy profiling of the platform during development is a necessity if we are to deliver platforms with the performance we require while satisfying our energy and thermal constraints.
Scenario-driven power analysis during platform development is most easily accomplished through the use of prototyping techniques or via hardware emulation, where we can simulate the power behavior of our complete system running under a full or representative workload. If we expect to be able to both analyze the power behaviour of the system and use that information to then make intelligent choices concerning hardware and software architecture and partitioning then virtual prototyping is the clear choice.
Virtual prototyping has been gaining in popularity and support over the last few years and has been very well adopted for performance tuning in multicore SoCs and for the early development of software, long before silicon and boards are available. By extending virtual prototyping to be power aware, we now have the ability to tune both power and performance concurrently while also addressing the overall energy efficiency of our software as well as the bring up of system power management.
Power aware virtual prototyping is enabled with system level IP power models — essentially power abstractions of an IP component that contain all relevant power-related characteristics for use in system-level design. The industry has been hard at work over the last couple of years extending the IEEE 1801 standard for use in system level IP power modelling. The latest revision of this standard (informally known as UPF3.0) has now entered the formal IEEE ballot stage and we expect it to be an approved IEEE standard by the end of 2015.
With the introduction of UPF 3.0 we now have the ability to model the salient power characteristics of IP components in an industry standard way and use those models to enable energy-aware system-level design methodologies, which subsequently allow us to perform scenario-driven power analysis of platforms very early in the design phase. As UPF 3.0 nears formal approval we can expect EDA and IP vendors to ramp support for this standard over the coming months.
With UPF 3.0 we will no longer require IP vendors to provide power models in 57 varieties and for the EDA companies, R&D resources now can be invested in the development of innovative and differentiating automation to improve time to (optimal) results, rather than support for the consumption of a multitude of home-grown power models. System-level IP power models by themselves are not really differentiating technology, and the ability of the industry to recognize this, address it and get a standard in place out in front of the ramp in demand will help avoid a repeat of the low power standards issues of the past.
As UPF 3.0 power models become increasingly more prevalent, we should expect to see the deployment of a wide selection of robust tools and methodologies that can take advantage of these models to enable scenario-driven exploration of hardware and software architectures that help address the power and performance duality issue.
System-level IP power models then become a key enabler to the delivery of differentiating platform architectures across a wide range of applications, including mobile, automotive, IoT, embedded, etc. These various platform types are all sensitive to power, and so energy efficiency is a critical design metric. Having a single system-level IP power modeling standard that can address power modeling for use in all types of design across a wide variety of process variants enables the investment in IP power modeling to be amortized across a wide variety of applications.
Enabling power- or energy-aware system-level design with industry standard support via UPF 3.0 goes a long way in helping the focus of low-power design to shift from the IP level to the system level. At that level we we can see much more of the problem, have the opportunity to make intelligent power-related decisions from a system perspective, and deliver significant improvements in energy efficiency.