Stimuli-Driven Power Grid Analysis

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A look at vector and vectorless approaches, and where each one works best.

The terms vector and vectorless modes are commonly used in the context of dynamic power grid (PG) analysis, but what do these terms mean? The PG dynamic simulator uses a design’s activity suite to compute the voltages and currents in the PG network. In vector mode, logic simulation is used to generate the complete activity suite. Vector mode is typically referred as a VCD (Value Change Dump). In vectorless mode, the PG analysis tool generates this activity suite.

The PG dynamic simulator cannot differentiate between an activity suite generated from either vector or vectorless mode. However, the quality of the dynamic PG analysis with respect to correlating with actual circuit operation is driven by the quality of the activity suite. Let’s take a look at the advantages and disadvantages of the two approaches.

The vector mode is more accurate, because the temporal relationships among the various gate components, especially across the flip-flop boundaries, are preserved. Figure 1 shows the sequence of gate activity for a VCD trace. In this example, the gates along the blue annotation line are active during the time interval of the dynamic PG analysis.  Note that there is a flip-flop along the set of gates that are in the activity suite.

Fig1_VCD_Activity_Trace
Figure 1. VCD Activity Trace

It is important that the sequencing of the gate firing incorporates the timing windows from the static timing analysis (STA) (Figure 2). The timing window provides a more accurate delay sequencing that accounts for both the gate-intrinsic and interconnects delays.

Fig2_STA_Windows
Figure 2. Static Timing Analysis Windows

Figure 3 shows a straightforward vectorless mode implementation that randomly selects gates to be included in an activity suite. The red lines denote the gates that have been included for this activity suite. As you can see, the correlation with actual circuit operation will be poor, since the activity suite incorporates fragments or gates from unrelated STA paths. In actual circuit operation, the probability of a gate triggering should be higher for fan-out gates than for unrelated gates.

Fig3_Vectorless_implementation
Figure 3. Vectorless implementation with random gate selection

Figure 4 shows another vectorless mode implementation that accounts for STA paths during the construction of the activity suite. Preference is given to fragments that comprise a STA path so as to preserve the combination logic correlation. The advantage of utilizing the STA information is that so-called false paths are pruned. However, the correlation across the flip-flop elements is lost—each clock period during the PG analysis is independent from every other clock period. For certain state machine design styles, such as a one-hot encoding, the sequential correlation will be poor.

Fig4_Vectorless_implementation-2
Figure 4. Vectorless implementation that accounts for STA paths

The disadvantage of the VCD approach is primarily a direct consequence of data unavailability, due to a variety of reasons. Logic simulation runs generate so much VCD data that writing it to disk significantly increases simulation runtimes, so most of the VCD data is routinely discarded. Even if the VCD data is available, the data typically arrives much too late to be incorporated into the PG analysis runs. In addition, VCD data size is often further reduced, since only the VCD vectors that will sufficiently stress the PG (have high power signatures) are retained (Figure 5). The end result is that VCD data coverage might not be good enough uncover potential PG issues.

Fig5_VCD_Power_Profiling
Figure 5. VCD Power Profiling

Vectorless mode, on the other hand, can construct vectors that increase the chance of uncovering potential PG issues by using such techniques as scheduling activity within a small region, or near weak regions of the PG network. Figure 6 shows an example where 3 STA path fragments have been constructed near such localized regions with a concentration of active gates. Region 1 has three gates active within the same time interval, while Region 2 has two gates active.

Fig6_Targeted_vectorless_mode
Figure 6. Targeted Vectorless Mode

In summary, then, while vector mode provides the best correlation with the actual circuit operation, vectors are usually difficult to obtain in sufficient variety. The vectorless mode is typically the default option. With sufficient care, such as incorporating the STA report, the correlation with respect to actual circuit operation can be improved. Other vectorless techniques being developed in the academic research community show potential for further enhancing the correlation with respect to actual circuit operation.

 

 




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