Stop Getting Burned By Power Consumption Surprises

Why it’s essential to gain early visibility into the power and thermal behavior of the platform.

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Very rarely these days do we get silicon back and find that we have missed our timing or test constraints by a significant margin. We have robust EDA tools, libraries and design methodologies in place to ensure that we can cleanly signoff against these constraints. However, we do continue to see too many unfortunate “surprises” in silicon related power (energy) consumption and thermal issues that can have a significant commercial impact.

We should no longer be getting surprised by power consumption. We have solid levels of robustness in the power related aspects of our EDA tools, libraries and our low power methodologies to ensure that we satisfy our power (energy) budgets. One possible cause for these surprises is failing to address power consumption and thermal issues early enough in our design cycle to ensure that we design-in energy efficiency from the outset rather than trying to recover an adequate low power physical implementation from a sub-optimal platform or sub-system architecture. The way in which a platform is used determines its energy consumption, and so visibility of both power consumption per power state as well as power state residency is necessary.

Low power design is not solely a physical implementation problem. It is a system design problem and should be addressed at all phases in the design cycle of a platform comprising complex hardware, software and system power management components. We essentially require a “low power continuum” to ensure that as we move from system level to silicon we have good visibility of the power behavior of our system under representative load, and that we can effectively manage the power, performance and thermal tradeoffs intelligently.This low power continuum comprises a number of parts including:

  • Power and energy aware architecture exploration and analysis from software to silicon;
  • Integration of thermal aware design methodologies for thermally throttled power management;
  • Platform power analysis at many levels of design abstraction with acceptable levels of accuracy;
  • Consistent and correlated power characterization and modelling for both exploration and signoff;
  • Seamless integration of low power design methodologies throughout the design flow;
  • Industry standard representation of power related information throughout the design flow, and
  • Ability to continuously refine the power intent as we refine the design description.

Taking a holistic view of low power system design is essential if we are to meet aggressive power and thermal constraints concurrently with the challenges presented by performance requirements and time to market pressure. Seamless integration of various low power methodologies enabled by industry standard representation of our data and models provides a solid platform upon which we can have confidence to make the key architectural decisions early in the design cycle that will yield the greatest benefit in terms of energy efficiency.

In addition, a tight coupling between power and thermal management of our platform enables thermal throttling of system power management. The algorithms we use for power management and for thermal management may well operate on different timescales (ns/10s ms up to 100s ms respectively). Being able to visualize the impacts in platform behavior — both from a power perspective and a thermal perspective, while operating under real or representative software load — is essential in establishing optimal system power management strategies and algorithms.

We know that decisions made during architecture exploration and software development have the greatest impact on energy efficiency, so we must be able to provide software and system-level design teams with visibility into the power and thermal behavior of the platform very early. Power-aware virtual prototyping certainly goes a long way toward that goal. However, we also need to be able to validate that the decisions we make during power-aware system-level design do in fact yield the benefits we are seeking, and so correlating system level power and thermal analysis results with analysis at lower (more detailed) levels of abstraction is vital. This is where emulation (particularly hybrid emulation) can play a big part by providing far more accurate levels of analysis of critical hot spots within the design.

For example, coupling Synopsys’ ZeBu emulation with virtual prototyping (Synopsys’ Virtualizer or Platform Architect products) creates a hybrid emulation solution that can be used to accelerate subsystem analysis and allow greater focus on specific hot spots. Emulation of an entire platform provides us with the ability to capture software driven activity profiles. These can then be used in more detailed (and accurate) power calculation and refinements in IP power characterization to yield more accurate power models for use in system level architecture exploration and analysis. This relatively tight loop that hybrid emulation offers provides an excellent mechanism for tuning the energy efficiency of a large complex SoC or platform operating under real or representative software loads by focusing on specific areas of interest within our scenario at a level of accuracy that is necessary.

Fine tuning our platform architecture for energy efficiency in this way gives us an excellent starting point for traditional low power physical implementation, during which we can continue to employ the tried and tested low power implementation techniques and methodologies to address mitigation of both dynamic and static power consumption. Recent developments in low power industry standards (IEEE 1801, IEEE 2415 and IEEE 2416) also help ensure interoperability between EDA tools, IP and these system level power aware design methodologies.

Industry support for the development of comprehensive low power system design tools and methodologies has been a major focus for a number of years. The adoption of power and thermal aware system level design and verification methodologies, together with their integration with existing low power implementation methodology, provides us with the confidence to help ensure we no longer need to deal with as many nasty post-silicon power surprises.