Emulation highlights from CDNLive Silicon Valley.
They say it takes a village to raise children and, as a dad of an 11-year-old girl, I can relate. Similarly, for system development and hardware-assisted verification, the overall ecosystem of users, use models, and partners is equally important. The recent CDNLive Silicon Valley event is a great example. The SoC and Hardware/Software track that my team and I were hosting featured NVIDIA, Netronome, AMD, and Teledyne Lecroy, plus MicroSemi/PMC twice! The discussions in the villages of Protium and Palladium as part of the System Development Suite were fun and fostered a great experience exchange.
The full set of CDNLive presentations can be found online. We kicked it off with an update on our recently introduced Palladium Z1 enterprise emulation platform, focusing on the throughput aspects I had discussed previously. There was quite some interesting discussion about the Palladium Z1’s industry-first capabilities. One of them is virtual target relocation—enabling the move of emulation fully into the datacenter by enabling physical connections to be as far away as 30 meters. Another one is advanced job re-shaping—allowing designers to pack jobs efficiently into the available resources, achieving the best utilization for multiple users with different job sizes. It’s like playing Tetris, as shown in the video below (click on the picture).
Melanie Bianchi from NVIDIA talked about their results applying the use model “Verification Acceleration” to verify NVIDIA’s NVLink high-speed interconnect with 5X to 10X greater bandwidth than PCIe. With silicon not available yet, a software model was created and put into an emulation-based verification environment using Palladium gFIFO/sFIFO technology to optimize transfers between the simulation host and emulation, increasing overall execution speed. They also were able to re-use the NVLink model from unit, to IP, to full chip verification.
Ron Swartzentruber from Netronome presented on “Design, Verification, and Emulation of an Island-Based Network Flow Processor,” specifically a large-scale 200Gbps network processor containing over 200 processors with multiple high-speed I/Os. Their use model is really system validation and performance analysis. Their objective was to emulate their design to find potential bottlenecks and guarantee system performance, as well as to enable software applications to run pre-silicon. A key result they are looking for is really the speed up of executing lots of networking packets—they are working towards a goal of 9000X over pure simulation.
AMD’s Alex Starr presented on “Emulation Productivity: Beyond the Specs.” He broke down the productivity that AMD wants to improve into the four aspects of hardware system, workflow, stimulus, and design. His talk was a great overview on how to make efficient use of emulation, concluding that many productivity aspects are within user control, while others are within vendor control, with specs of gate count and frequency only being a small part of the story. Efficiently planned flows and procedures can help keep productivity high. Alex went through how many emulation system limitations can be partially mitigated, some cannot, but that generally planning emulation work to play to the strengths of different systems is important. As an example, he cited that FGPA-based prototyping is good for software teams, not necessarily great for early design bring-up.
John Wiedemeier presented for one of our partners, Teledyne Lecroy, on “Ubiquitous PCI Express Verification from Simulation Through Post-Silicon Development.” Their protocol analyzer for PCIe can be connected through a SpeedBridge interface to designs running on a Palladium platform, allowing to verify pre-silicon designs with post-silicon validation methodologies, and to apply live traffic testing for corner-case analysis of designs under test.
Riad Ben Mouhoub representing MicroSemi talked about the balance of emulation and FPGA in his presentation “Meeting Complex Multiprocessor System-on-Chip Co-Verification and FW Development Schedules Using Emulation and Prototyping Platforms.” He summarized the reasons for choosing Palladium Z1 as a combination of smaller footprint compared to its predecessor, dynamic relocation of target pods for external connections, faster wave uploads for debug for which they saw times 5X faster than Palladium XP, the switch to optical connections, faster compile times, and reduced power consumption. Key capabilities that made them choose Protium included the common front-end flow with Palladium, resulting in easier maintenance of builds maintenance and the ability of the Protium hardware to be used with any custom flow, requiring no ASIC RTL modifications. He also emphasized how there is no need to manually intervene for timing closure, the users’ ability to generate as many clocks as they need, and the large variety of peripherals and memories to quickly connect the DUT to a realistic environment. They can also use traditional on-chip debug tools or port the design back to Palladium, force signals, use monitors, and utilize the memory backdoor access for debug and quick firmware deposits that are even compatible with Palladium Z1 scripts. This presentation would be quite instructive for users that need to balance hardware verification and software development needs with emulation and FPGA-based prototyping.
Also representing MicroSemi, Smitha Kaginele and Murthy Hari described their work to efficiently create lots of tests for SoC verification that then can be executed on simulation and emulation. They used Perspec System Verifier to generate portable stimulus using legal randomized test scenarios with constraints captured in centralized CSV files in which all parameters are random unless explicitly constrained. The use of this approach enables separation of roles between modeler and test writer, with the modeler encapsulating architectural constraints into the model and the test writer not being required to focus on constraint details. They found it easy to generate complex scenarios using Perspec Composer’s drag-and-drop composition and scenario completion with the graphical scenario representation enabling collaboration. They also found the debug capabilities very productive, allowing scenario visualization and debug with embedded software traces, and integrated this approach into regression planning, creation, and maintenance.
So CDNLive again showed that all is well in the Cadence village of hardware-assisted development. The presentations I mentioned can be found here. The large variety of use models shown at CDNLIve Silicon Valley alone include verification acceleration (NVIDIA), in-circuit emulation (Netronome, AMD), and in-circuit acceleration (AMD), as well as software development and system validation (MicroSemi). The two main quarters of FPGA-Based Prototyping and Emulation work well together among them and interact with their neighbors generating tests (Perspec System Verifier shown by Microsemi), software-based verification with the Incisive platform, and ecosystem partners for testing (Teledyne Lecroy).