Reworking Established Nodes


New technology markets and a flattening in smartphone growth has sparked a resurgence in older technology processes. For many of these up-and-coming applications, there is no compelling reason to migrate to the latest process node, and equipment companies and fabs are rushing to fill the void. As with all electronic devices, the focus is on cost-cutting. But because these markets are likely ... » read more

Moore’s Law: Toward SW-Defined Hardware


Pushing to the next process node will continue to be a primary driver for some chips—CPUs, FPGAs and some ASICS—but for many applications that approach is becoming less relevant as a metric for progress. Behind this change is a transition from using customized software with generic hardware, to a mix of specialized, heterogeneous hardware that can achieve better performance with less ene... » read more

The Week In Review: Design


Tools Synopsys debuted a tool to replay RTL simulation data on a gate-level netlist for power analysis the company says is accurate within 5% of signoff. The tool, PowerReplay, is design to be used in combination with PrimeTime PX gate-level power analysis for earlier and faster generation of gate-level switching data. IP ClioSoft launched a design reuse ecosystem for searching and com... » read more

Secret Sauce To Make Design Reuse A Reality


In a globally competitive landscape, IP reuse and effective team collaboration play a crucial role in product success. But if one considers the complex dynamics of all the recent advances in technology, the insatiable appetite for consumer electronics coupled with the design cost and time-to-market pressures on designers, one would not be unjustified in assuming that the problem of design reuse... » read more

Visual Design Diff


A document, whether it is stored as a simple text file or as a word processor formatted file, is often a living entity that is constantly evolving. A user may create a first draft, revise it multiple times, have other team members review it and make alterations, and refine it over time to keep up with new information and requirements. What has changed since the last revision becomes very import... » read more

Challenges Grow For IP Reuse


As chip complexity increases, so does the complexity of IP blocks being developed for those designs. That is making it much more difficult to re-use IP from one design to the next, or even to integrate new IP into an SoC. What is changing is the perception that standard [getkc id="43" kc_name="IP"] works the same in every design. Moreover, well-developed [getkc id="100" kc_name="methodologie... » read more

Quality Issues Widen


As the amount of semiconductor content in cars, medical and industrial applications increases, so does the concern about how long these devices will function properly—and what exactly that means. Quality is frequently a fuzzy concept. In mobile phones, problems have ranged from bad antenna placement, which resulted in batteries draining too quickly, to features that take too long to load. ... » read more

Big Data On Wheels


By Jeff Dorsch & Ed Sperling All kinds of chips are going into driver-assisted and autonomous cars. On one side are arrays of sensors, which are generating huge amounts of data about everything from lane position and proximity to other cars to unexpected objects in the road. On the other side are the chips required to process that data at blazing speed. As the market for PCs and mobil... » read more

No More Easy IP Money


The semiconductor intellectual property ([getkc id="43" kc_name="IP"]) industry is two decades old, but questions are still being asked about what's wrong with it and what needs to be fixed. Normally these kinds of issues are reserved for fast-moving, young industries, not one that is the backbone of semiconductors. Design reuse has become an indispensable part of the design of nearly all el... » read more

DAC Day Three: UVM, Machine Learning And DFT Come Together


The industry and users have a love/hate relationship with UVM. It has quickly risen to become the most used verification methodology and yet at the same time it is seen as being overly complex, unwieldy and difficult to learn. The third day of DAC gets started with breakfast with Accellera to discuss UVM and what we can expect to see in the next 5 years. The discussion was led by Tom Alsop, pri... » read more

← Older posts