tag: engineering change orders

Speeding Up Design Closure
By Ed Sperling - 23 Aug, 2023 - Comments: 0

Increasing complexity and smaller process nodes make it far more difficult to achieve design closure for chips. There are more physical effects to model, including noise, cross-talk, and double switching effects, all of which can slow the design process. Solaiman Rahim, vice president of engineering for Synopsys’ EDA Group, talks about why it’s so important to analyze violations in design, ... » read more

Dealing With ECOs In Complex Designs
By Ed Sperling - 22 Jan, 2020 - Comments: 0

Namsuk Oh, R&D principal engineer at Synopsys, talks about the impact of more corners and engineering change orders, how that needs to be addressed in the flow to close timing, and how dependencies can complicate any changes that are required. » read more

Changing The Design Flow
By Ed Sperling - 07 Aug, 2018 - Comments: 0

Synopsys’ Michael Jackson talks with Semiconductor Engineering about why it’s becoming necessary to fuse together various pieces of digital design. https://youtu.be/AOWh4wjw-ps » read more

The Final Days…Getting To Sign-Off Faster With Calibre
By Mentor, a Siemens Business - 06 Mar, 2017 - Comments: 0

With deadlines looming, the design flow between router output and final tape release can be stressful and frustrating. By combining a focused set of commands into macros, the Calibre YieldEnhancer tool enables designers to create customized, automated flows for engineering change order (ECO) filling, passive device insertion, custom fill to increase densities, jog removal, and via enhancements.... » read more

Re-Coloring ECO Changes With Calibre Multi-Patterning
By Mentor, a Siemens Business - 21 Sep, 2016 - Comments: 0

Engineering change orders (ECOs) can wreak havoc on multi-patterning (MP) coloring (and time to market) if not dealt with quickly and efficiently. Design teams working on MP designs need a complete ECO enablement solution, before recoloring issues consume resources and destroy schedules. The Calibre Multi-Patterning tool provides smart, automated support for recoloring designs after ECO impleme... » read more

More Than Moore
By Ed Sperling - 21 Aug, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at Open-Silicon; Patrick Soheili, vice president and general manager of IP Solutions at eSilicon; Brandon Wang, engineering group director at Cadence; John Ferguson, product manager for DRC applications at Mentor Graphics; and Kevin Kranen, d... » read more

The Week In Review: June 21
By Ed Sperling - 21 Jun, 2013 - Comments: 0

By Ed Sperling Mentor Graphics rolled out emulation-ready verification IP for MIPI camera and display-based protocols. The VIP enables stimuli generated by UVM and SystemC-based environments and applies them to a design under test (DUT) running in the emulator. Synopsys introduced a tool for implementing and verifying functional engineering change orders, including matching, visualization ... » read more

Engineering Change Orders Revisited
By Ed Sperling - 29 Nov, 2012 - Comments: 0

By Ed Sperling The perennial nightmare of the marketing head reporting that a customer will buy a design—but only if it fits into a specific power envelope or has better performance or I/O—is all too familiar to engineering teams. In theory, using more third-party IP should help alleviate this problem because the IP can be changed out relatively easily. The reality, though, is that it�... » read more

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