Design And Verification Survey Results

Previously I have blogged about the verification surveys that Real Intent runs at tradeshows throughout the year.  We find it useful to track trends in tool needs and reveal what are the pain points designers are feeling.  I last reported to you, a year ago, in the blog article Clocks and Bugs, where I focused on clock-domain crossing (CDC) errors causing re-spins. This year, I would like ... » read more

Techniques For FSM Design And Verification

Large system-on-chip (SoC) designs contain many finite state machines (FSMs) that interact with data paths, memories, and other components. Although FSMs are critical building blocks many designers lack an understanding of their role and impact on design quality and validation effort. FSMs are a source of functional bugs in SoCs. They can cause poor timing, power, and performance. Although v... » read more