EDA, IP Sales Up 8%


The EDA sector continues to exhibit solid growth, increasing 8% to $2.2262 billion in Q3, up from $2.0937 billion in the same period in 2016, according to the most recent stats from the ESD Alliance Market Statistics Service. The four-quarter moving average was up 11.5%, year over year. While all of the numbers were up, two areas showed extraordinary growth. One involved Japan, which showed ... » read more

The Week In Review: Design


M&A Synopsys acquired one-time programmable non-volatile memory IP provider Kilopass. Founded in 2001, Kilopass' 1T and 2T bitcell IP supports up to 4-Mbit OTP instances in 180-nm to 7-nm process technologies. The acquisition will add to Synopsys' growing OTP NVM portfolio: last October, Synopsys acquired Sidense, another provider of the technology. Terms of the deal were not disclosed. ... » read more

A Simple Way To Improve Automotive In-System Test


The remarkable growth in automotive IC design has prompted a focus on ISO26262 functional safety compliance, which includes both high-quality manufacturing test and a minimum stuck-at test coverage of 90% for in-system test. Designers must also control IC test data volumes, test application times, and test costs. A new test point technology that improves in-system test coverage and reduces patt... » read more

Turning Down The Power


Chip and system designers are giving greater weight to power issues these days. But will they inevitably hit a wall in accounting for ultra-low-power considerations? Performance, power, and area are the traditional attributes in chip design. Area was originally the main priority, with feature sizes constantly shrinking according to Moore's Law. Performance was in the saddle for many years. M... » read more

Machine Learning’s Growing Divide


[getkc id="305" kc_name="Machine learning"] is one of the hottest areas of development, but most of the attention so far has focused on the cloud, algorithms and GPUs. For the semiconductor industry, the real opportunity is in optimizing and packaging solutions into usable forms, such as within the automotive industry or for battery-operated consumer or [getkc id="76" kc_name="IoT"] products. ... » read more

Improving In-System Test With Tessent VersaPoint Test Point Technology


This paper describes a new versatile test point technology called VersaPoint, which has been developed specifically to work with designs implementing mixed EDT/LBIST methodologies to reduce EDT pattern counts and improve Logic BIST (LBIST) test coverage. VersaPoint test points can reduce compressed pattern counts 2X to 4X beyond compression alone and improve LBIST test coverage beyond what is p... » read more

Blog Review: Jan. 10


Rambus' Aharon Etengoff explains the Meltdown and Spectre CPU vulnerabilities and why they could negatively affect the semiconductor industry for decades. Cadence's Paul McLellan has an explainer on Meltdown and how it's an unintended consequence of a processor behaving as intended. Mentor's Ruben Ghulghazaryan and Jeff Wilson investigate using machine learning to predict post-deposition ... » read more

Could Liquid IP Lead To Better Chips?


Semiconductor Engineering sat down to discuss the benefits that could come from making IP available as abstract blocks instead of RTL implementations with Mark Johnstone, technical director for Electronic Design Automation for [getentity id="22499" e_name="NXP"] Semiconductor; [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; Bryan Bowyer, director of ... » read more

Auto Chip Test Issues Grow


By Jeff Dorsch & Ed Sperling Semiconductor suppliers are flocking to the automotive chip market to gain share in fitting out the connected car and the autonomous vehicle. But before those chips are sold to automotive manufacturers and Tier 1 suppliers, they must be tested and certified to meet stringent industry standards. This is no ordinary testing, though. Assisted and autonomous v... » read more

Getting Serious About Chiplets


Demand for increasingly complex computation, more features, lower power, and shorter lifecycles are prompting chipmakers to examine how standardized hard IP can be used to quickly assemble systems for specific applications. The idea of using chiplets, with or without a package, has been circulating for at least a half-dozen years, and they can trace their origin back to IBM's packaging schem... » read more

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