Measuring FinFETs Will Get Harder

The industry is gradually migrating toward chips based on finFET transistors at 16nm/14nm and beyond, but manufacturing those finFETs is proving to be a daunting challenge in the fab. Patterning is the most difficult process for finFETs. But another process, metrology, is fast becoming one of the biggest challenges for the next-generation transistor technology. In fact, [getkc id="252" kc_n... » read more

Inside X-ray Metrology

Chipmakers are ramping up a new class of chip architectures, such as 3D NAND and finFETs. Measuring and characterizing the tiny structures in these technologies is a major challenge. It will not only take the traditional metrology tools, but also various X-ray techniques. To get a handle on X-ray metrology, Semiconductor Engineering recently discussed the trends with the following experts: ... » read more

Searching For 3D Metrology

In the previous decade, chipmakers made a bold but necessary decision to select the [getkc id="185" kc_name="finFET"] as the next transistor architecture for the IC industry. Over time, though, chipmakers discovered that the finFET would present some challenges in the fab. Deposition, etch and lithography were the obvious hurdles, but chipmakers also saw a big gap in metrology. In fact,... » read more