The Week In Review: Design

Siemens to by Mentor Graphics; tools for test; reset domain crossing.

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M&A

Siemens plans to buy Mentor Graphics for $4.5 billion in cash. The move, if approved by regulators, would greatly expand Siemens’ capabilities in multi-physics design and embedded software for everything from semiconductors to automotive wiring harnesses. The transaction is expected to close in the second quarter of 2017.

Tools

Mentor Graphics uncorked a new product to measure the defect coverage of any test applied to an analog or mixed-signal circuit. The tool, Tessent DefectSim, measures the effects of opens, shorts, extreme variations, and user-defined defects modeled within a layout-extracted or schematic netlist as well as measuring a circuit’s tolerance to defects.

Synopsys expanded its test and yield analysis solution targeting finFET-specific defects to the 7nm node. Features include improved slack-based cell-aware test to increase defect coverage, finFET SRAM defect modeling and test algorithms, plus defect isolation to specific areas within design cells to diagnose yield issues.

Aldec launched the latest version of its Riviera-PRO functional verification tool. The company says it provides performance improvements in SystemVerilog compilation and simulation and includes a solution for collecting functional verification data in Open Source VHDL Verification Methodology (OSVVM).

Cadence’s Modus test solution now supports the ARM Memory Built-In Self Test (MBIST) interface for safety-critical designs. The two companies completed silicon validation using a Cortex-A73 processor.

Real Intent debuted new software for comprehensive reset domain crossing (RDC) sign-off. The tool, Meridian RDC, verifies that asynchronous resets that are crossing reset domains will not cause metastability when resets are activated or de-activated, reconverging synchronized resets are functionally correlated, and asynchronous resets are glitch-free.

IP

eMemory’s security-enhanced NeoFuse IP was demonstrated on TSMC’s 10nm FinFET process, along with IP design kits for product design-in. The qualification of NeoFuse IP in TSMC’s 16nm FFC process will be done in early 2017, with completion in 10nm FinFET in the second half of 2017.

Brite Semiconductor’s YouPHY-DDR DDR4, DDR3/LPDDR3 subsystem was silicon proven on SMIC’s 40nm low leakage process. According to the silicon data, the data rate of YouPHY-DDR reached 2400Mbps in DDR4 protocol and 2133Mbps in DDR3/LPDDR3.

Asiczen released UVM-based System Management Bus verification IP.

Deals

Imagination adopted Synopsys’ STAR Memory System with multi-memory bus (MMB) processor for memory built-in self-test (BIST) and repair of its new MIPS I6500 processor. Synopsys also announced a number of automotive semiconductor suppliers are deploying its synthesis-based test solution, including Elmos Semiconductor, MegaChips, Micronas, Renesas Electronics, and Toshiba.

Ansys, the High Performance Computing Center (HLRS) of the University of Stuttgart, and Cray hit a new record for scaling Ansys’ Fluent CFD software to 172,032 cores on the Cray XC40 supercomputer located at HLRS, running at 82% efficiency.

Mentor Graphics inked a multi-year license agreement with ARM to gain early access to a broad range of ARM Fast Models, Cycle Models and related technologies. Mentor will have access to all ARM Fast Models for the ARMv7 and ARMv8 architectures across all ARM Cortex-A, Cortex-R, Cortex-M cores, GPUs and System IP, in addition to engineering collaboration on further optimizations.