Andes IPO; automotive physical IP; energy processing unit; PCIe with AXI bridge; certifications and IP for TSMC 7, 12nm.
Andes Technology went public this week on the Taiwan Stock Exchange with an initial stock listing of 40,611,915 shares at a price of NT$65.10 (USD $2.12) per share. The shares began trading March 14, 2017, under the TWSE ticker symbol “6533.TWO.” Andes plans to use the proceeds to expand the company’s R&D effort, to fuel international expansion into the U.S. and Europe and to increase its competitiveness in China, Korea, and Japan.
ARM announced a platform of dedicated automotive ARM Artisan physical IP for TSMC 16FFC. Development and qualification of the IP meets ISO 26262 for functional safety and AEC-Q100 Grade 1. ARM also released the safety package for its latest-generation C/C++ compilation toolchain, ARM Compiler 6. The package consists of the safety-certified ARM Compiler toolchain, compiler qualification kit and long-term support and maintenance service.
Synopsys launched an interface IP portfolio for TSMC’s new 12nm FinFET Compact (12FFC) process which includes USB, DisplayPort, PCI Express, DDR, LPDDR, SATA, MIPI, Ethernet and HDMI.
Sonics unveiled the second product in its energy processing unit line, which introduces a new component, the cluster controller, to support definition of complex power states at the system level and implement those states by closely coordinating the actions of up to 256 lower-level power grain controllers.
Performance-IP introduced IP for improved memory performance in SoCs. The IP, Memory Request Optimizer, is an advanced prefetch engine which reduces memory latency between the memory subsystem and the SoC client by providing on-demand data delivery and increasing the bandwidth.
PLDA debuted new IP for integrating AXI and PCIe 4.0 blocks. According to PLDA, the bridge prevents AXI deadlock and delivers full PCIe performance on the AXI side, while reducing the risk of errors in the AXI block.
Silicon Creations uncorked 0.25Gb/s to 12.7Gb/s multiprotocol SerDes PMA IP for TSMC’s 40LP process, as well as several PLL products for the 7nm process. The PMA supports over 30 protocols, and the PLL products include a 5µW, 32kHz IoT PLL, low-jitter fractional frequency synthesizer, area optimized core voltage integer PLL, and high bandwidth deskew PLL.
Analog Bits announced front-end design kits for low-power IP for SERDES, PLL, PVT sensors and POR on TSMC’s latest 7nm process. The design kits are available for customers with early access to Analog Bits IP.
Comcores launched IP for Radio-Over-Ethernet to be used in wireless fronthaul. The IP features L1 offload and time-sensitive-network (TSN) MAC targeting FPGA and ASIC devices.
Cadence’s digital, signoff and custom/analog tools were certified for TSMC’s new 12nm FinFET Compact (12FFC) process as well as for the new TSMC 7nm process. Corresponding process design kits are available.
Cadence also developed an integrated design flow for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology which provides design and analysis capabilities and modeling of cross-die interactions for mobile and IoT applications.
Synopsys’ custom design tools were certified with UMC’s 14nm FinFET process. The two companies created an interoperable process design kit (iPDK) for the process.
Ansys tools were certified for a variety of multi-die analyses including extraction, power and reliability, signal and power integrity, and thermal and electromagnetic interference on TSMC’s 7nm process and Integrated Fan-Out (InFO) packaging technology.
Mentor Graphics’ Calibre and Analog FastSPICE platforms were certified for TSMC’s 12FFC process as well as the TSMC 7nm V1.0 process. According to the company, the current V1.0 release has shown a significant Calibre DRC runtime improvement compared with the initial releases.
Compliance firm SGS-TÜV Saar certified the ISO 26262 compliance of Mentor’s Software Tool Qualification Report for its Questa Simulation, Verification Management and Clock-Domain Crossing products.
ZTE licensed Arteris’ cache coherent interconnect IP and network-on-chip fabric IP for use in its advanced SoCs, citing optimal mixing of ARM- and PCIe-based traffic in complex embedded systems.