TSMC: Onward to 5nm

Foundry is aggressively pushing to the next node using third-generation EUV.

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TSMC’s financial results for the Q4 of 2015 were released in January and showed an 8.5% revenue drop compared to the previous year, and a 3.5% decrease compared to Q3 (all in NT$). For the full year though, TSMC said it had again achieved record sales, with revenue for the full year up over last year by 10.6% in NT$ (5.7% in US$).

President and co-CEO Mark Liu reported that TSMC sees a reduction in high-end smartphone demand for the first quarter of 2016, but beyond that it expects to be back to a growth trajectory. For 2016, TSMC is forecasting a world smartphone shipment unit growth rate of 8%; PCs minus 3%; tablets minus 7%; and digital consumer electronics minus 5%.

Smartphones continue to be a major driving force in the industry and TSMC is working on ramping up new technology nodes very quickly. By historic standards the 20nm process was an incredibly fast ramp, as shown in Figures 1 and 2 below. Starting with Q3 of 2015, TSMC combined reporting of 20nm and 16nm, so this makes it a bit difficult to tease out exactly how fast 16nm is ramping. The red curve in Figure 1 below jumped to an incredibly quick start, but now with the combination of 16nm appears to be falling more on top of the previous 28nm curve. Given the dramatic change in the underlying devices at 16nm, this still seems fairly impressive.

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Figure 1. Percent wafer revenue per technology ramp from introduction.

President and co-CEO CC Wei indicated that TSMC had successfully ramped up production of its 16nm process at the start of Q3 2015, and that manufacturing indices, such as yield and cycle time, were achieved three to four months sooner than at the 20-nanometer node and are ahead of plan. Q4 2015 also saw in addition to 16-FinFET Plus, completion in the development for 16-FFC, which is TSMC’s low-power and low-cost version of the 16nm process. As customers accelerate their technology migration to 16nm, TSMC is also anticipating a significant drop in demand for the 20nm process in 2016. Last year, Wei said that TSMC expected to have more than 50 product tape-outs in 2015 in 16nm FinFET with high-volume production starting in Q3 and meaningful revenue contribution for Q4. So it appears that TSMC is hitting those targets.

Last year, TSMC said that it expected 20nm to contribute 20% of the total wafer revenue for 2015. SVP and CFO Lora Ho reported that 20nm/16nm had in fact contributed 20% of the total wafer revenue for 2015 and 24% of the total wafer revenue for Q4 of 2015. She also stated that TSMC remains confident that the combined revenue contribution from these two technologies will continue to grow meaningfully in 2016. 28nm contributed 28% of the total wafer revenue for 2015. The graph in Figure 2 clearly shows the ascension of the 20nm/16nm technologies and the decline in total percentage of wafer revenue for 28nm. Again, 20nm was very quick from launch to 20% wafer revenue.

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Figure 2. Percent wafer revenue per technology node over the last 10 years.

In Q4 of 2014, 51% of TSMC’s wafer revenue was from 28nm and 20nm wafers combined and that has actually dropped in percentage terms to 49% for Q4 of 2015 (and that was up from 48% for Q3 of 2015). Some of this perhaps has to do with the blending of the 20nm/16nm technologies and the incredibly fast initial ramp of 20nm.

Last year Mark Liu said that TSMC’s qualification schedule for the end of the year (2015) for 10nm remained the same with expected volume production in 2017. On this January’s call he said, “Our 10-nanometer technology development is on track. We are currently in intensive yield learning mode in our technology development. Our 256-megabit SRAM is yielding well. We expect to complete process and product qualification and begin customer product tape-outs this quarter.”

That would seem to push the introduction of new technologies even faster than the typical cadence shown in Figure 2. Liu also said, “Our 7-nanometer technology development progress is on schedule as well. TSMC’s 7-nanometer technology development leverage our 10-nanometer development very effectively. At the same time, TSMC’s 7-nanometer offers a substantial density improvement, performance improvement and power reduction from 10-nanometer.”

On top of the high-end smartphone and high-performance computing markets, TSMC sees a third sector emerging for automated driver assistance systems (ADAS), and it is planning to support these three areas with both the 10nm and 7nm technology families. 5nm is planned to be out about two years after 7nm. TSMC claims that significant progress has been made on EUV, with likely insertion into the 5nm process. It is now installing third-generation EUV tools in its fabs.

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Table 1. Percent of revenue from market segments.

Lora Ho said, “On a full-year basis, revenue from communication increased 16% year over year and represented 61% of our total wafer revenue. Industrial and standard also saw 22% year-over-year growth, driven by increasing usage of MCU, Flash controller and the power management IC.” For comparison purposes, Table 1 above shows relative fourth quarter numbers over the past decade.

TSMC continues to hit its targets and is aggressively scheduling new technologies out to 5nm. It should have some very interesting presentations at this year’s North America Symposiums happening in San Jose, Boston and Austin this month.


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