Combining power domain manipulation on top of system-level tests for low-power verification.
In a recent blog post, Steve Carlson talked about the use of software-driven tests to support concurrent power and performance analysis. Generation of software-driven tests is one of the key technologies that will be enabled by the upcoming standard from Accellera’s Portable Stimulus Working Group (PSWG). Portable stimulus spans functional verification as well as performance validation, so PSWG-compliant software-driven testing is a key technology for ensuring that low-power designs work properly. Powering domains within a system-on-chip (SoC) design up and down must not disrupt the specified functionality.
Low-power verification is truly a system-level problem; the full range of power domains is visible only with the full SoC. Generating system scenarios that represent realistic use cases is a key part of the Accellera portable stimulus vision. This standard will define a format for capturing abstract models of verification intent from which commercial EDA tools can generate tests to run on the full range of verification platforms. These tests include results checking and coverage metrics in addition to stimulus. The platforms supported include virtual platforms, simulation, acceleration, in-circuit emulation (ICE), FPGA prototyping, and silicon in the bring-up lab.
Using portable stimulus to verify intended low-power behavior is actually a combined solution. The SoC verification team first develops the abstract model, aided by libraries and methodology from the EDA vendor. The vendor’s tools can then automatically generate an extensive set of software-driven tests that can be downloaded into the SoC’s embedded processors and run on any or all of the verification platforms. Coverage is predicted at generation time and verified at run time. The resulting system-level coverage can be combined with traditional metrics such as code coverage and SystemVerilog coverage for a comprehensive view of verification progress.
At this point, the verification team knows that the SoC operates properly across a wide range of scenarios that represent real use cases and how the chip will be used in actual applications. However, nearly every SoC has low-power design features that involve turning on and off power domains, and specific combinations of domains. Minimizing power consumption is important for a wide range of SoCs, most obviously to preserve battery life for portable applications. However, governmental regulations may establish power limitations even for non-portable devices. Even server SoCs are relevant, since studies have shown that datacenters spend more money on power than hardware over the lifetime of servers.
All of these factors drive low-power features into SoCs, and it is critical to verify that these features do not compromise the functionality of the designs. Formal analysis can verify specific aspects of low-power design structures, but it is also essential to verify that the full range of system-level tests can run across the full range of power variations. Turning off a particular power domain must not affect unrelated functionality, while the domain must power up properly when needed for a scenario to complete. This is where portable stimulus provides an ideal solution by combining power domain manipulation on top of the system-level tests. The flow is shown in the following diagram:
The upper left portion of this diagram shows the capture of verification intent in a portable stimulus model and the generation of use-case scenarios. The lower left shows that many aspects of low-power design for the SoC are captured in the Unified Power Format (UPF) file, now standardized as IEEE 1801. A model of low-power behavior can be created from this power intent file. The portable stimulus tool combines the scenarios to generate software-driven tests that execute system-level functional scenarios while power domains are powered up and down. These tests are run on any verification platform desired, and system-level coverage is collected to show how well the overall verification plan has been satisfied.
Portable stimulus is a natural and effective method to verify the system-level aspects of low-power design precisely because of its ability to capture abstract verification requirements and automatically generate use-case tests. This flow fits within the Accellera vision for portable stimulus, but interested verification teams need not wait for the PSWG to complete its work and release a standard. Cadence’s Perspec System Verifier and its supporting libraries provide a software-driven solution to low-power verification today, well aligned with both the Accellera vision and the upcoming portable stimulus standard. Please visit the Cadence site to learn more.