A systematic methodology to verify latch-up prevention and ESD protection of 2.5D and 3D ICs.
2.5D/3D integrated circuits (ICs) have evolved into an innovative solution for many IC design and integration challenges. As shown in figure 1, 2.5D ICs have multiple dies placed side-by-side on a passive silicon interposer. The interposer is placed on a ball grid array (BGA) organic substrate. Micro-bumps attach each die to the interposer, and flip-chip (C4) bumps attach the interposer to the BGA substrate. In 3D ICs, dies are mounted on top of each other. Communication between dies and communication with the substrate are handled by interfaces using through-silicon vias (TSVs).
Fig. 1: 2.5D versus 3D IC designs.
This combination of dies within the package presents unique verification challenges that challenge electronic design automation (EDA) tools originally designed for 2D ICs. While automated flows for IC reliability verification are well-established for regular 2D ICs, 2.5D and 3D integration presents new challenges in both design and verification. For example, one issue that must be resolved is the accurate recognition and treatment of pads in a 2.5/3D IC layout. In 2D ICs, all pads act as input/output (IO) interfaces that communicate with the outside world through the package pins. Because there are multiple dies in 2.5D and 3D integration, some pads are used to communicate signals between dies through micro-bumps, TSVs, and the interposer, and do not communicate with the outside world at all (figure 2). This key difference in 2.5D/3D ICs requires that designers differentiate between those two categories of pads by classifying them as either external IOs (connect to the outside world) or internal IOs (do not connect to the outside world). This distinction is critical to accurate and efficient 2.5/3D IC verification.
Fig. 2: External IOs versus internal IOs.
Innovative functionality and verification strategies are now enabling automated reliability verification of 2.5/3D ICs. A systematic methodology can be formulated to address these challenges and verify latch-up prevention and electrostatic discharge (ESD) protection of 2.5D and 3D ICs [1,2] in an automated process using EDA advanced reliability verification tools. We’ll look at how automated latch-up and ESD protection verification can be implemented in 2.5/3D IC design verification flows using the Calibre PERC reliability platform from Siemens Digital Industries Software [3].
Latch-up is modeled as a short circuit (low-impedance path) that can occur in an integrated circuit (IC), as shown in figure 3. A latch-up path is typically created by current injection or over-voltage, but even after the initiating event ends, the path remains. Latch-up may lead to destruction due to over-current resulting from interactions between parasitic devices (PNP and NPN). The parasitic structure is usually equivalent to a silicon-controlled rectifier (SCR) or PNPN structure that acts as a PNP and an NPN transistor stacked next to each other. When one transistor is conducting, the other one begins conducting, too. As long as the structure is forward- biased, current flows through it.
Fig. 3: Latch-up condition (source: Wikipedia).
Latch-up protection is accomplished through design rules that define the constraints required to prevent the conditions under which latch-up can occur. There are two key types of latch-up prevention design rules—fundamental and advanced [4,5].
Fundamental rules are local latch-up design rules that focus on physical dimension rules associated with the parasitic pnpn network, such as minimum p+ to n-well spacing, minimum n+ to n-well spacing, guard ring type, minimum guard ring spacing, and minimum guard ring width.
Advanced latch-up design rules fall into two main categories: external and mixed voltage.
Because advanced latch-up design rules require knowledge of external injection sources and voltage, any protection scheme must be able to capture this information from the design. In 2D ICs, the most common method is the use of manual layout markers. As you might expect, accurately managing a manual layout markers methodology is even more difficult and time-consuming in 2.5D and 3D IC designs. Finding a way to automatically capture this information without the use of markers is the first requirement for an effective 2.5/3D IC latch-up verification strategy.
Accurate classification of internal vs. external IOs in 2.5D/3D ICs is also essential in latch-up verification because internal IOs have a low latch-up risk. This low risk allows engineers to safely ignore latch-up verification for these IOs and focus only on external IOs.
Fundamental latch-up design rules must be addressed independently in 2.5/3D ICs because different dies have different local latch-up rules. These differences exist because dies can be designed on different technology nodes from different foundries. Consequently, local latch-up physical verification is addressed by applying the appropriate foundry design rule checks (DRC) for every die separately and analyzing problems accordingly.
The major challenges in automating latch-up verification in 2.5D/3D ICs are related to the advanced latch-up design rules (i.e., external and mixed-voltage). These challenges are summarized in the following points [1]:
Given the layout of each die and the interposer as input, automated 2.5/3D IC latch-up verification flows are based on differentiation between external IOs and internal IOs, without the use of layout markers to drive the analysis. While it is preferable to have complete layouts for dies that are free from basic DRC and layout vs. schematic (LVS) errors, this is not an absolute requirement. It is also possible to work with partial layouts as long as they contain all the geometries that must be verified and the right connectivity to die ports.
The methodology contains two flows: (1) a topology- aware flow for external latch-up design rules, and (2) a voltage-aware flow for mixed voltage latch-up design rules. In both flows, we start from the assembly level, as demonstrated in figure 4.
Fig. 4: Latch-up verification methodology.
The assembly level provides the complete picture for how the dies are connected to each other, so this is where we perform the analysis to differentiate between external and internal IOs (figure 5). The goal is to filter out the internal IOs so we can perform appropriate latch-up verification on the external IOs only. The Calibre PERC tool automatically generates a layout netlist that describes the connections between dies, which are treated as black boxes—that is, it generates a netlist for the assembly without the devices or nets that make up the inside of the dies. Next, it identifies die-to-external pad connections (external IOs) on the layout netlist. At the end, it stores info for every die with its external IO names on die-level. This info is used later in die-level analyses.
Fig. 5: Assembly-level identification of external IOs.
The goal of the topology-aware latch-up flow (figure 6) is to address external latch-up design rules for every die. The Calibre PERC tool automatically identifies any latch-up injectors and corresponding layout geometries in this flow. It then performs external latch-up DRC measurements on relevant geometries and reports violations for debugging.
Fig. 6: Latch-up verification – die level (topology-aware flow).
The goal of the voltage-aware latch-up flow (figure 7) is to address mixed-voltage latch-up design rules for every die. First, the Calibre PERC tool propagates voltages through devices from defined external ports to internal nodes in the design, enabling identification of direct/indirect connectivity of latch-up injectors. Layout geometries of the identified latch-up injectors are captured automatically. The tool then measures the relevant geometries for mixed-voltage latch-up DRC, and reports violations for debugging.
Fig. 7: Latch-up verification – die level (voltage-aware flow).
The following checks are the types of checks that can be addressed:
External latch-up design rules (figure 8):
Fig. 8: Examples of external latch-up design rules.
Mixed-voltage latch-up design rules (figure 9):
Fig. 9: Examples of mixed-voltage latch-up design rules.
ESD events cause severe damage to ICs due to a sudden and unexpected flow of electrical current between two electrically charged objects caused by contact, an electrical short, or dielectric breakdown. An ESD event may cause a metal melt, junction breakdown, or oxide failure. ESD events can damage an electronic component at any stage of its production or use, if not properly prevented.
Ensuring your IC design has the ability to withstand ESD events without incurring damage or failure is extremely important in IC circuit design and verification. Multiple protection schemes are available to avoid or mitigate ESD damage [6,7]. Designers must add proper ESD protection schemes in both the schematic (early in the design cycle) and layout stages. Of course, checking these ESD protection circuits to ensure they are adequate and properly implemented before fabrication is an essential part of design reliability verification [8,9]. ESD protection design rules are included in design rule manuals to enable designers to verify the presence of appropriate ESD protection from a topological perspective. Figure 10 demonstrates a common ESD protection scheme.
Fig. 10: Typical ESD protection scheme.
To ensure adequate ESD robustness, designers must evaluate ESD protection for proper construction and interconnect robustness to verify the circuitry can fully absorb and process any ESD strike. Two metrics are evaluated for interconnect robustness: point-to-point (P2P) parasitic resistance and current density (CD). Measuring P2P resistance requires calculating the interconnect resistance between a given external pad (or cell port) and the corresponding ESD device pin to report the combined resistance. Measuring CD requires calculating the CD in every polygon on every metal/via layer from start pin (or port) to end pin (or port), which is done by injecting an ESD current at an external pad and measuring CD on all interconnect polygons up to the ESD device pin.
From an ESD verification perspective, we cannot treat 2.5D/3D ICs simply as a group of independent 2D ICs connected together. ESD devices can span multiple dies; when that occurs, they must be combined for correct evaluation. We must also classify ESD events for different IO types when evaluating ESD protection. External IOs are connected to the package pins and face more ESD events than internal IOs [10]. Similar to 2D ICs, external IOs are affected by both human body model (HBM) and charged device model (CDM) ESD events. However, internal IOs are affected by far fewer HBM and CDM events. By identifying where internal IOs are located in the 2.5D/3D IC, ESD design engineers can place appropriately smaller ESD protection circuits, which in turn translates into significant savings in die area and cost without sacrificing overall ESD protection robustness.
The major challenges for automating ESD verification in 2.5D/3D ICs can be summarized in the following points [11]:
An automated 2.5/3D IC ESD verification methodology requires the following to be readily available: ESD constraints, assembly layout, die layouts, parasitic resistance rule decks, and LVS rule decks. As demonstrated in figure 11, this methodology contains three stages (assembly-level, die-level, and complete 2.5D/3D IC design-level).
Fig. 11: ESD verification methodology.
In the first stage, the Calibre PERC reliability platform extracts the relevant ESD data from the assembly layout needed to capture the effect of interposers/interfaces, as shown in figure 12.
Fig. 12: ESD assembly-level verification.
The second stage extracts the relevant ESD data from the die layouts (figure 13). This process is repeated for each die, because dies can be designed on different technology nodes and manufactured using different foundries, so each die must be treated separately.
Fig. 13: ESD die-level verification.
The third stage performs ESD verification on the complete 2.5D/3D IC design level to perform data merging, structural ESD checks, and total P2P computations, as shown in figure 14.
Fig. 14: ESD design-level verification (complete 2.5D/3D IC).
The Calibre PERC platform uses the layout extraction performed in the assembly-level and die-level analyses, respectively, to create layout netlists for the assembly (i.e., interposer/interfaces) and all dies, and the complete 2.5D/3D IC netlist is generated by combining all these netlists into one design-level netlist. This single netlist enables the structural ESD checks shown in figure 14 to be performed at the complete 2.5D/3D IC design level.
There are three categories of 2.5/3D IC ESD protection schemes: external IOs, internal IOs, and supply. The purpose of all ESD checks is to identify missing/wrong/correct protection schemes, based on a user-defined structure for each category. Table 1 lists the ESD checks that can be performed for each IO type vs. the ESD protection scheme.
Table 1: ESD protection checks
The ESD structural checks report ESD protection schemes as missing, wrong, or correct. For missing/wrong ESD protection schemes, problematic external IOs and internal IOs are reported as violations, which can then be debugged. For correct ESD protection schemes, relevant external and internal IOs are reported for information only, and the routing is validated to verify it can handle an ESD event by computing the total P2P parasitic resistance for every correct protection route, and checking current density.
Latch-up prevention and ESD protection are essential elements in IC designs. While automated verification of the accuracy and capacity of an ESD protection circuit is an established process for 2D IC layouts, 2.5D/3D IC design ESD protection verification must overcome additional challenges that, until now, have resisted automation. Innovative automated 2.5D/3D IC latch-up prevention and ESD protection verification using tools like the Calibre PERC reliability platform can not only reduce verification cycles, but also improve the quality and reliability of these designs. Ensuring the reliability and product life of 2.5/3D IC designs helps ensure they deliver the value and functionality the market demands.
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