September 2014 - Page 4 of 11 - Semiconductor Engineering

Executive Insight: Lip-Bu Tan
By Ed Sperling - 22 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down with [getperson id="11693" comment="Lip-Bu Tan"], president and CEO of [getentity id="22032" e_name ="Cadence"], to discuss his outlook on EDA, Moore’s Law and his strategy for investing in startups around the world. What follows are excerpts of that conversation. SE: What’s worrying you these days? Tan: There are a couple of things. One is the complex... » read more

What Will That DSA Template Do, Anyway?
By Katherine Derbyshire - 22 Sep, 2014 - Comments: 0

As directed self assembly techniques make the transition from line and space test patterns to the more complex structures seen in real devices, modeling is emerging as a significant issue. How will the co-polymers behave in the presence of a particular template pattern? While several laboratory-scale modeling methods exist, most are too computationally expensive to be used for large area str... » read more

Who Changes Us
By Anne Cirkel - 19 Sep, 2014 - Comments: 2

Most of us have one of more people that had a huge impact on our life. For me one of those is my former husband, Klaus Cirkel. We met when we were still at university, RWTH Aachen, in western Germany. I was slowly making my way through the metallurgy curriculum. Well, Klaus was the total opposite. He was driven and his drive was infectious. He motivated me to expedite my degree then to take the... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 19 Sep, 2014 - Comments: 0

Gartner predicts that by 2016 smartwatches will comprise about 40% of consumer wristworn devices. Gartner said that nine out of the top 10 smartphone vendors have entered the wearables market to date or are about to ship a first product, while a year ago only two vendors were in that space. The eBeam Initiative announced the completion of its third annual survey. In one of the highlights of ... » read more

The Week In Review: Design
By Ed Sperling - 19 Sep, 2014 - Comments: 0

Tools Open-Silicon uncorked a 28Gbps SerDes evaluation platform, complete with board, test chip and characterization data, which it says will speed up and simplify development of chips for 100G networks. The chip utilizes PHY IP from Semtech. IP Synopsys rolled out MIPI C-PHY verification IP that utilizes a three-phase coding technique for faster camera, display and SoC interfaces. http://... » read more

Why Multi-Die Integration Really Is On Its Way
By Steve Schulz - 19 Sep, 2014 - Comments: 0

Admit it. You’ve heard a lot about 3D IC’s for years now, and it’s starting to get old. Lots of talk but not much action, you say? Maybe it will never happen, you say? Well, perhaps it’s time to reassess the current situation, reevaluate emerging needs, and reset our “3D” paradigm for the coming multi-die imperative. The problems associated with 3D IC (stacked die) are real and v... » read more

2014 eBeam Survey Results
By eBeam Initiative - 18 Sep, 2014 - Comments: 0

An industry-wide poll highlights what the industry is thinking about EUV and mask writing at advanced nodes. To view the poll, click here. » read more

Improve Failure Analysis Success Rate With Layout-Aware Diagnosis
By Mentor, a Siemens Business - 18 Sep, 2014 - Comments: 0

In this whitepaper, we explore how a layout-aware diagnosis is a powerful tool for both failure analysis engineers, who find the root cause of a particular failing die, and for yield engineers, who need sets of diagnosis data to find the systematic yield limiters across the life of the product. Logic-based scan test diagnosis is an established software-based methodology for finding the defec... » read more

Why Investments At Advanced Nodes Matter
By Ed Sperling - 18 Sep, 2014 - Comments: 0

Despite all the talk about rising costs of development, uncertainties about lithography and talk about the death of Moore’s Law, a record number of companies are developing chips at 16nm/14nm. That may sound surprising, but asking why that’s happening is probably the wrong question. The really critical question is what they’re going to do with those chips. What’s become quite evident... » read more

One-On-One: Mark Bohr
By Mark LaPedus - 18 Sep, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss process technology, transistor trends, chip-packaging and other topics with Mark Bohr, a senior fellow and director of process architecture and integration at Intel. SE: Intel recently introduced chips based on its new 14nm process. Can you briefly describe the 14nm process? Bohr: It’s our second-generation, tri-gate technology. So it has al... » read more

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