January 2019 - Page 2 of 13 - Semiconductor Engineering

EDA Grabs Bigger Slice Of Chip Market
By Brian Bailey - 31 Jan, 2019 - Comments: 0

EDA revenues have been a fairly constant percentage of semiconductor revenues, but that may change in 2019. With new customers creating demand, and some traditional customers shifting focus from advanced nodes, the various branches of the EDA tool industry may be where sticky technical problems are solved. IC manufacturing, packaging and development tools all are finding new ways to handle t... » read more

Chips&Media: Design and Verification of Deep Learning Object Detection IP
By Mentor, a Siemens Business - 30 Jan, 2019 - Comments: 0

Chips&Media, a leading provider of high-performance video IP for SoC design, took a unique approach to designing their latest IP for detecting objects in real time. They decided to adopt a new High-Level Synthesis (HLS) flow to implement their deep learning algorithm. But, they would have an RTL team create this algorithm, using traditional tools and another team would employ the Catapult H... » read more

January ’19 Startup Funding: $100M+ Rounds Abound
By Jeff Dorsch - 30 Jan, 2019 - Comments: 0

Sixteen companies received private funding rounds of $100 million or more during the month of January, with two privately held companies, Infor and Verily Life Sciences, taking in rounds of $1.5 billion and $1 billion, respectively. The market segments represented in the January rounds were varied. Multiple companies using artificial intelligence technology in their offerings and cloud-based... » read more

Shifting the Burden of Tool Safety Compliance from Users to Vendor
By OneSpin Solutions - 30 Jan, 2019 - Comments: 0

The security, safety and performances of autonomous vehicles, railways, aerospace, nuclear power plants and medical devices rely on electronic systems and their hardware components. Engineers use advanced software tools to develop complex hardware. Tools may malfunction, generate erroneous output and ultimately introduce or fail to detect systematic hardware faults that could cause hazardous ev... » read more

Clock Domain Crossings in the FPGA World
By Aldec - 30 Jan, 2019 - Comments: 0

Clock domain crossing (CDC) issues cause significant amount of failures in ASIC and FPGA devices. As FPGA complexity and performance grows, the influence of CDC issues on design functionality grows even more. This paper outlines CDC issues and their solutions for FPGA designs. Various design techniques are presented together with real-life examples for Xilinx and Intel FPGA devices. More import... » read more

Blog Review: Jan. 30
By Jesse Allen - 30 Jan, 2019 - Comments: 0

Cadence's Paul McLellan provides a primer on embedded memory types, their tradeoffs, and the emerging technologies to keep an eye on. Mentor's Matthew Ballance takes a look at how Portable Stimulus can help create better virtual sequences. Synopsys' Taylor Armerding takes a look at what the next year holds for open source, from changes in license terms to the impact of GDPR and a broader ... » read more

A Simplified Way to Debug IIP Designs and SoC
By Synopsys - 30 Jan, 2019 - Comments: 0

Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. It's not uncommon for an engineer to run the verification test on what appears to be the main design problem, only to find the problem in the dump. Traditional debug techniques don't always help to localize the issue. This whitepaper... » read more

Building Security Into RISC-V Systems
By Ed Sperling - 30 Jan, 2019 - Comments: 0

Semiconductor Engineering sat down with Helena Handschuh, a Rambus fellow; Richard Newell, senior principal product architect at Microsemi, a Microchip Company; and Joseph Kiniry, principal scientist at Galois. Part one is here. (This is the second of two parts.) L-R: Joseph Kiniry, Helena Handschuh, Richard Newell. SE: Some of the new applications for hardware designs are tied to AI, d... » read more

Manufacturing Bits: Jan. 29
By Mark LaPedus - 29 Jan, 2019 - Comments: 1

Thermal lithography Using a technique called thermal scanning probe lithography, New York University (NYU) and others have reported a breakthrough in fabricating 2D semiconductors. With the technology, researchers have devised metal electrodes with vanishing Schottky barriers on 2D semiconductors based on molybdenum disulfide (MoS₂). Thermal scanning probe lithography, sometimes called t-... » read more

System Bits: Jan. 29
By Jeff Dorsch - 29 Jan, 2019 - Comments: 0

Quantum physics make hybrid semiconductors glow Hybrid semiconducting materials have quantum properties capable of bringing significant changes to light-emitting diode lighting and monitors, along with photovoltaic solar cells, researchers at the Georgia Institute of Technology report. Physical chemists worked with halide organic-inorganic perovskite (HOIP), which combines a crystal lattice wi... » read more

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