Aging Models: The Basis For Predicting Circuit Reliability

Identifying the mechanisms that trigger future chip reliability issues, plus ways to implement aging models.


Today, many products are based on high-performance electronic systems and integrated circuits (ICs), and the importance of these elements is ever-increasing. A certain tension arises here as these applications often call for a large amount of processing power and reliability. The processing power can best be supplied with highly scaled semiconductor technologies. However, these manufacturing technologies were developed for consumer products. They are considered relatively susceptible to reliability problems when used in long-lasting or safety-critical products, in sustained operation or under harsh operating conditions, such as in automotive or industrial electronics. Because endurance tests in the laboratory are very expensive, the reliability of ICs must be ensured as far as possible with the use of simulations. A wide range of failure mechanisms must be taken into account here.

Hot carrier injection (HCI) and bias temperature instability (BTI) are two of these mechanisms. These involve the reliability of integrated transistors and result in continuous shifting of the properties of the transistors rather than in a sudden failure. Nonetheless, their appearance can negatively affect the circuit reliability.

HCI is caused by a flowing drain current, in which moving charge carriers break up the bonds between silicon and hydrogen at the boundary between the transistor channel and gate dielectric. Charges are captured as a result, which reduces the carrier mobility in the channel and thereby the flowing drain current. BTI is divided into negative BTI (NBTI) on PFETs and positive BTI (PBTI) on NFETs. At elevated temperature and gate voltage (positive for PBTI and negative for NBTI), charge carriers can enter into the gate dielectric and charge traps that are present due to process irregularities. These charges in the gate dielectric increase the absolute value of the threshold voltage of the transistor in question. If the voltage at the gate is reduced, the traps can be discharged again, which is referred to as recovery.

The impacts of HCI and BTI on ICs can be investigated with aging simulations. Various vendors of EDA software provide such simulations as an extension to circuit simulations, thereby enabling prediction of the circuit behavior after a specific period of use in a defined usage scenario, the mission profile. Important input factors for aging simulations are the models that describe HCI and BTI aging for the underlying transistors. So far, the developers of commercial EDA software have offered to some extent proprietary or highly simplified models with their tools. Which of these models best matches a specific technology can hardly be determined in advance. However, custom aging models can be integrated into the simulators by means of specific interfaces. With a clever approach, it is possible to achieve previously unavailable consistency between different EDA tools.

Aging models can in principle be implemented in two ways. On one hand, aging can be modeled by modifying the parameters of the underlying compact model of the transistor. On the other hand, equivalent circuits can emulate aging by introducing additional circuit elements, mainly controlled sources, around the unchanged transistor. Regardless of the implementation, various requirements must be taken into account in the definition of aging models.

(1) The degradation of electrical characteristics, such as VTH, GMAX, IDLIN and IDSAT, is usually measured according to JEDEC standards under constant stress (DC bias and constant temperature). For simulations, however, it is necessary to support transient voltage waveforms.

(2) Useful simulation times and the lifespans required of ICs differ by more than ten orders of magnitude. One common solution to this problem is to work with typical usage scenarios. A circuit is simulated via this scenario, and it is then assumed that this scenario will be run through repeatedly and regularly until the predefined lifespan has been reached. An aging model must therefore enable an extrapolation from a simulation to the lifespan.

(3) The model precision and complexity must be traded off. Two methods of varying scope are available here in the form of empirical approaches, which describe the electrical characteristics, and physical approaches, which are based on microscopic mechanisms. The selection of which electrical characteristics must be incorporated into the model offers further opportunities for customization.

Today, transistor aging models that are customized to specific semiconductor technologies, accuracy requirements, and EDA environments appear to be appropriate solutions for IC designers. Future developments will probably be influenced by the Compact Modeling Coalition (CMC) of the Silicon Integration Initiative (Si2), which is currently developing standardized aging equations and a standard simulator interface for reliability.

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