How to close the gap between the design and test worlds to improve coverage and shorten time to market.
Shu Li, business development manager at Advantest, zeroes in on the communication gap between engineers on the design side and the manufacturing/test side, why it exists, and what needs to be done to bridge that gap in order to speed up and improve test quality.
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What about virtual testing? Doesn’t that solve part of the problem? What about converting back the tester pattern to eVCD, allowing the designer to run this in their test bench/Verilog bench?
The WGL and STIL to ATE translation process has been automated for quite a few years now. VCD/eVCD to ATE has recently been automated with auto-timing discovery, auto-cyclization, auto-assignment of ATE formats, and auto-generation of ATE programs. Furthermore, the debugging task has been automated with pre-silicon virtual testing (or re-simulation) as Yovav mentioned. The true virtual test methodology applies ATE patterns directly to the design netlist without translating tester pattern back to eVCD. Plus, all these can be done upfront by the design verification team who has an upper hand on device knowledge and netlist simulation (vs test team).