Author's Latest Posts


System Bits: Oct. 8


The next big thing in particle accelerators Stanford University engineers have helped create what may be the next big thing in particle accelerators – and it fits on a fingertip. In a project that included scientists from the U.S. Department of Energy’s SLAC National Accelerator Laboratory, a linear accelerator two miles long, accelerators energized charged particles to accomplish a ran... » read more

Experts At The Table: How To Improve IP Quality


By Ann Steffora Mutschler Semiconductor Engineering sat down to discuss the best ways to improve the quality of design IP with Piyush Sancheti, vice president of product marketing at Atrenta; Chris Rowen, Cadence Fellow and former CTO at Tensilica; Gene Matter, senior applications manager at Docea Power; Warren Savage, president and CEO of IPextreme; and Dan Kochpatcharin, deputy director of ... » read more

Power/Performance Bits: Oct. 1


First Computer Based On Carbon Nanotubes Pointing toward a new generation of energy-efficient electronics, a team of Stanford engineers has built a basic computer using carbon nanotubes (CNT), a semiconductor material that has the potential to launch a new generation of electronic devices that run faster, while using less energy, than those made from silicon chips. People have been talking ... » read more

System Bits: Oct. 1


Origami-Shaped Antennas A Georgia Tech-led research team is working to develop a unique approach to making extremely compact and highly efficient antennas and electronics based on principles derived from origami paper-folding techniques to create complex structures that can reconfigure themselves by unfolding, moving and even twisting in response to incoming electromagnetic signals. The str... » read more

Experts At The Table: How To Improve IP Quality


By Ann Steffora Mutschler Semiconductor Engineering sat down to discuss the best ways to improve the quality of design IP with Piyush Sancheti, vice president of product marketing at Atrenta; Chris Rowen, Cadence Fellow and former CTO at Tensilica; Gene Matter, senior applications manager at Docea Power; Warren Savage, president and CEO of IPextreme; and Dan Kochpatcharin, deputy director of I... » read more

More Rigor, Please


By Ann Steffora Mutschler Semiconductor companies are embracing a single-platform strategy for their SoC designs, but sifting through the options can be quite a feat. While not wildly different from the traditional derivative approach, a single-platform strategy can mean different things to different companies. Sometimes it refers to a platform that is already successful in one application ... » read more

More Test Needed For Integrated IP


By Ann Steffora Mutschler As the use and reuse of design IPs and cores has reached approximately 70% of the content of an SoC, the need for both pre- and post-silicon test has increased. On the pre-silicon side, test comes in the form of verification IP. Driving the addition of more strenuous test approaches on this side is a combination of forces that impact design, noted Tom Hackett, prod... » read more

System Bits: Sept. 24


Printing nanostructures with self-assembling material A multi-institutional team of engineers from the University of Illinois at Urbana-Champaign, the University of Chicago and Hanyang University in Korea has developed a new approach to the fabrication of nanostructures for the semiconductor and magnetic storage industries. The approach combines top-down advanced ink-jet printing technology... » read more

Power/Performance Bits: Sept. 24


Generating electricity from sewage Stanford University researchers have come up with a new way to generate electricity from sewage using naturally-occurring “wired microbes” as mini power plants, producing electricity as they digest plant and animal waste. Calling their invention a ‘microbial battery,’ the researchers hope one day it will be used in places such as sewage treatment p... » read more

Mask Data Prep Issues Compounding At 20nm


By Ann Steffora Mutschler When it comes to mask data prep—the step in the design and manufacturing flow that occurs just after optical proximity correction (OPC)—challenges have continued to rise with the subsequent moves to smaller geometries. This is driven by the scaling demands of delivering about a 50% area shrink from node to node on a two-year cycle, and thus dictates the lithog... » read more

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