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Ann Mutschler

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Ann Mutschler is senior executive editor at Semiconductor Engineering.

Author's Latest Posts

System Bits: Sept. 17
By Ann Mutschler - 17 Sep, 2013 - Comments: 0

Multicore memory management According to MIT researchers, it may be time to let software rather than hardware manage high-speed on-chip memory caches. Traditionally, managing the caches has required fairly simple algorithms that can be hard-wired into the chips but as multiple cores in SoCs proliferate, cache management becomes much more difficult. As such, MIT’s Department of Electric... » read more

Power/Performance Bits: Sept. 17
By Ann Mutschler - 17 Sep, 2013 - Comments: 0

Harvesting energy from light In a finding they believe could improve technologies for generating electricity from solar energy and lead to more efficient optoelectronic devices used in communications, researchers from the University of Pennsylvania and Duke University have demonstrated a new mechanism for extracting energy from light. They said the process is much more efficient than conven... » read more

Experts At The Table: Next-Generation IP Landscape
By Ann Mutschler - 13 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

Power Optimization Requires Higher-Level Thinking
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler With consumer demand—much of it for power sensitive mobile devices—driving the bulk of semiconductor design activity, it would seem obvious that the way chips are designed would have changed to reflect that. But have they? From an EDA perspective, the term ‘system level’ is used to mean ‘product level’ but this may not be enough, especially when it come... » read more

How Secure Are Low-Power Techniques?
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

As a chip designer, you and your team have done the best job possible to optimize power in your SoC, likely utilizing all of the low power techniques at your disposal. The chip tapes out, gets implemented into systems and it’s a success! Then the call comes that your chip has been hacked within the system it’s in and you and your team are left shaking your heads in wonder. I can imagine ... » read more

Low-Power CPUs Hitting Their Stride In The Datacenter
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler Without a doubt, the cloud has and continues to change the nature of the datacenter, particularly the requirements the infrastructure has to deliver. Diane Bryant, senior vice president and general manager of the Datacenter and Connected Systems Group at Intel, noted during a Webcast last week, “The infrastructure must change in support of cloud-based services.�... » read more

Power Optimization Requires Higher-Level Thinking
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler With consumer demand—much of it for power sensitive mobile devices—driving the bulk of semiconductor design activity, it would seem obvious that the way chips are designed would have changed to reflect that. But have they? From an EDA perspective, the term ‘system level’ is used to mean ‘product level’ but this may not be enough, especially when it come... » read more

Power Grid Analysis Heats Up At 20nm
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler Do a simple Internet search for the term ‘power grid analysis’ and most of the results are academic sources. However, given the physics of either planar or finFET at 20nm and below, the power grid will see significant impacts. Overall, there are a number of technical implications of migrating from 28nm down to 20, 16 or 14 nm, with further impacts of moving fro... » read more

System Bits: Sept. 10
By Ann Mutschler - 10 Sep, 2013 - Comments: 0

Enabling flexible touchscreens While transparent conductors make touchscreens possible, the cost and the physical limitations of the material these conductors are usually made of are hampering progress toward flexible touchscreen devices but a research collaboration between the University of Pennsylvania and Duke University has shown a new a way to design transparent conductors using metal nan... » read more

Power/Performance Bits: Sept. 10
By Ann Mutschler - 10 Sep, 2013 - Comments: 0

Using DNA to assemble transistors from graphene Graphene is a sheet of carbon atoms arrayed in a honeycomb pattern, just a single atom thick. It could be a better semiconductor than silicon – if we could fashion it into ribbons 20 to 50 atoms wide. Could DNA help? Stanford chemical engineering professor Zhenan Bao, believes it could. Bao and her team of researchers hope to solve a problem... » read more

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