Author's Latest Posts


More Rigor, Please


By Ann Steffora Mutschler Semiconductor companies are embracing a single-platform strategy for their SoC designs, but sifting through the options can be quite a feat. While not wildly different from the traditional derivative approach, a single-platform strategy can mean different things to different companies. Sometimes it refers to a platform that is already successful in one application ... » read more

More Test Needed For Integrated IP


By Ann Steffora Mutschler As the use and reuse of design IPs and cores has reached approximately 70% of the content of an SoC, the need for both pre- and post-silicon test has increased. On the pre-silicon side, test comes in the form of verification IP. Driving the addition of more strenuous test approaches on this side is a combination of forces that impact design, noted Tom Hackett, prod... » read more

System Bits: Sept. 24


Printing nanostructures with self-assembling material A multi-institutional team of engineers from the University of Illinois at Urbana-Champaign, the University of Chicago and Hanyang University in Korea has developed a new approach to the fabrication of nanostructures for the semiconductor and magnetic storage industries. The approach combines top-down advanced ink-jet printing technology... » read more

Power/Performance Bits: Sept. 24


Generating electricity from sewage Stanford University researchers have come up with a new way to generate electricity from sewage using naturally-occurring “wired microbes” as mini power plants, producing electricity as they digest plant and animal waste. Calling their invention a ‘microbial battery,’ the researchers hope one day it will be used in places such as sewage treatment p... » read more

Mask Data Prep Issues Compounding At 20nm


By Ann Steffora Mutschler When it comes to mask data prep—the step in the design and manufacturing flow that occurs just after optical proximity correction (OPC)—challenges have continued to rise with the subsequent moves to smaller geometries. This is driven by the scaling demands of delivering about a 50% area shrink from node to node on a two-year cycle, and thus dictates the lithog... » read more

System Bits: Sept. 17


Multicore memory management According to MIT researchers, it may be time to let software rather than hardware manage high-speed on-chip memory caches. Traditionally, managing the caches has required fairly simple algorithms that can be hard-wired into the chips but as multiple cores in SoCs proliferate, cache management becomes much more difficult. As such, MIT’s Department of Electric... » read more

Power/Performance Bits: Sept. 17


Harvesting energy from light In a finding they believe could improve technologies for generating electricity from solar energy and lead to more efficient optoelectronic devices used in communications, researchers from the University of Pennsylvania and Duke University have demonstrated a new mechanism for extracting energy from light. They said the process is much more efficient than conven... » read more

Experts At The Table: Next-Generation IP Landscape


By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

Power Optimization Requires Higher-Level Thinking


By Ann Steffora Mutschler With consumer demand—much of it for power sensitive mobile devices—driving the bulk of semiconductor design activity, it would seem obvious that the way chips are designed would have changed to reflect that. But have they? From an EDA perspective, the term ‘system level’ is used to mean ‘product level’ but this may not be enough, especially when it come... » read more

How Secure Are Low-Power Techniques?


As a chip designer, you and your team have done the best job possible to optimize power in your SoC, likely utilizing all of the low power techniques at your disposal. The chip tapes out, gets implemented into systems and it’s a success! Then the call comes that your chip has been hacked within the system it’s in and you and your team are left shaking your heads in wonder. I can imagine ... » read more

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