Author's Latest Posts


AI Buildout Makes HPC Simulation More Challenging


Simulations of semiconductors and systems are becoming bigger, more complex, and increasingly necessary, mirroring everything that is happening to the hardware itself — particularly in AI data centers. The move beyond monolithic chips to multi-die assemblies now requires solving some thorny multi-physics challenges, such as thermal and power delivery, which are increasingly difficult to mo... » read more

Harnessing Silicon Lifecycle Management For Chip Security


Silicon lifecycle management is starting to be used in ways that extend well beyond its original mission of ensuring a chip functions to spec throughout its expected lifetime. While tracking aging effects and component failures are still important, the technology also is being deployed to proactively monitor, authenticate, and respond to potential threats in real-time. In fact, not applying ... » read more

Optimizing AI Workloads For Edge Computing


Experts At The Table: Semiconductor Engineering gathered a group of experts to discuss how some AI workloads are better suited for on-device processing to achieve consistent performance, avoid network connectivity issues, reduce cloud computing costs, and ensure privacy. The panel included Frank Ferro, group director in the Silicon Solutions Group at Cadence; Eduardo Montanez, vice president an... » read more

The Real-World Impact Of Silicon Lifecycle Management On Chip Architectures


Silicon lifecycle management (SLM) is transforming chip architectures, empowering designers to build smarter, more resilient, and secure semiconductor devices by leveraging data from manufacturing to end of life in the field. That data can be used to improve future designs, reduce margin, and continuously optimize performance and power efficiency throughout a chip's lifetime. Moreover, under... » read more

Power Integrity And Voltage Issues Get Harder To Detect And Solve


Voltage and power integrity are becoming increasingly critical and challenging for chip designers and architects, regardless of which process technology they are using or which market they are targeting. An explosion of features vying unevenly for current is increasing the number of constraints and possible interactions that engineers need to sort through to ensure reliability. These include... » read more

Moving AI Workloads To The Edge


Experts At The Table: Semiconductor Engineering gathered a group of experts to discuss how some AI workloads are better suited for on-device processing to achieve consistent performance, avoid network connectivity issues, reduce cloud computing costs, and ensure privacy. The panel included Frank Ferro, group director in the Silicon Solutions Group at Cadence; Eduardo Montanez, vice president an... » read more

Thermal, Mechanical, And Material Stresses Grow With Die Stacking


Managing thermal and mechanical stress in multi-die assemblies will require a detailed knowledge of how and where a device will be used, how it will be packaged, and where stresses could cause problems at any point during its expected lifetime. This includes everything from workload-dependent thermal gradients to mechanical and electrical stress, which may become more pronounced over time wi... » read more

Multiple Challenges Emerge With Physical AI System Design


Physical AI holds the promise of making everything from robots to a slew of mobile edge devices much more interactive and useful, but it will significantly alter how systems are designed, verified, and monitored. Physical AI systems need to work both independently and together. They need the ability to make decisions quickly and locally, typically using much less power than other types of AI... » read more

New Approaches To Limit Cyberattacks On Hardware


The number and value of cyberattacks on semiconductors is rising, but new approaches to designing and packaging chips could put a significant dent in those figures. Semiconductor-related cybersecurity attacks have multiplied more than six times since 2022, according to a report by cyber intelligence firm CloudSEK. These attacks have cost the semiconductor industry an estimated $1.05 billion ... » read more

Silicon IP Continues Steady Growth Path


EDA and silicon IP revenue increased 8.6% to $5.089 billion in Q2 2025, up from $4.6855 billion in Q2 2024, according to the ESD Alliance. Total EDA revenue growth was assisted by impressive results in the CAE category, the largest tool sector, which showed 17.2% growth over Q2 2024. “It was another good quarter overall," said Walden C. Rhines, executive sponsor of the SEMI Electronic Desi... » read more

← Older posts Newer posts →