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Brian Bailey

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Brian Bailey is Technology Editor/EDA for Semiconductor Engineering.

Author's Latest Posts

SoC Power Grid Challenges
By Brian Bailey - 14 Jul, 2016 - Comments: 7

The consumption of power and dissipation of heat within large SoCs has received a lot of attention recently, but that is only part of the issue. Power also has to be reliably delivered onto and around the system. This is becoming increasingly difficult, and new nodes are adding to the list of challenges. "If we were building chips where there was only a single Vdd and Vss then it is not that... » read more

No More Easy IP Money
By Brian Bailey - 14 Jul, 2016 - Comments: 2

The semiconductor intellectual property ([getkc id="43" kc_name="IP"]) industry is two decades old, but questions are still being asked about what's wrong with it and what needs to be fixed. Normally these kinds of issues are reserved for fast-moving, young industries, not one that is the backbone of semiconductors. Design reuse has become an indispensable part of the design of nearly all el... » read more

Abundant Change Ahead
By Brian Bailey - 06 Jul, 2016 - Comments: 1

There is nobody who would question the amazing ride that semiconductors have been on for the past 50 years. It has been described as the longest running exponential that humankind has ever been a part of—and it is not over yet. Still, the future is very likely to be substantially different from the past. It is almost natural for us to see a trend and assume it will continue. There have bee... » read more

Can Verification Meet In The Middle?
By Brian Bailey - 30 Jun, 2016 - Comments: 0

Since the dawn of time for the EDA industry, the classic V diagram has defined the primary design flow. On the left hand side of the V, the design is progressively refined and partitioned into smaller pieces. At the bottom of the V, verification takes over and as you travel up the right-hand side of the V, verification and integration happens until the entire design has been assembled and valid... » read more

Will Open-Source Work For Chips?
By Brian Bailey - 30 Jun, 2016 - Comments: 2

Open source is getting a second look by the semiconductor industry, driven by the high cost of design at complex nodes along with fragmentation in end markets, which increasingly means that one size or approach no longer fits all. The open source movement, as we know it today, started in the 1980s with the launch of the GNU project, which was about the time the electronic design automation (... » read more

Decoding The Brain
By Brian Bailey - 22 Jun, 2016 - Comments: 1

At the Design Automation Conference this year, Lou Scheffer, principal scientist for the Howard Hughes Medical Institute, gave a visionary talk entitled Learning from Life: Biologically Inspired Electronic Design. Scheffer is an IC design guy who came through Stanford and Caltech and worked for HP and [getentity id="22032" e_name="Cadence"] before switching to the medical field eight years a... » read more

Near-Threshold Computing
By Brian Bailey - 16 Jun, 2016 - Comments: 2

The emergence of the Internet of Things (IoT) has brought a lot of attention to the need for extremely low-power design, and this in turn has increased the pressure for voltage reduction. In the past, each new process node shrunk the feature size and lowered the nominal operating voltage. This resulted in a drop in power consumption. However, the situation changed at about 90nm in two ways. ... » read more

System-Level Verification Tackles New Role
By Brian Bailey - 15 Jun, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, vice president of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_nam... » read more

Menta Embeds FPGA Programmability
By Brian Bailey - 14 Jun, 2016 - Comments: 0

What constitutes a startup can be a matter of the market segment you are going after and the type of product that you are building. Within [getkc id="7" kc_name="EDA"], we often think of the lifetime of a company being just a few years between when an opportunity is identified, to a product being built and getting the first few customers and then getting gobbled up by one of the big three. But ... » read more

DAC Day Four: Excitement And Risk
By Brian Bailey - 09 Jun, 2016 - Comments: 0

One thing that was new to DAC this year, was an art exhibit. These were pieces of artwork related to our industry, such as chip plots, or more abstract ideas based on design data or analyses. They received many more entrants than their wildest dreams and had to choose a winner from over 80 pieces, but the grand prize was won by a 3D model of a finFET by David Freid of Coventor. This piece was ... » read more

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