Author's Latest Posts


Embedded FPGA Timing


Namit Varma, senior director of Achronix’s India Technology Center, explains how to time an eFPGA, what can go wrong, what are the different clocking scenarios, and what impact variation has on the process. https://youtu.be/Jq4XUKnniB4 » read more

IoT Meets ML


AI and machine learning are the next big things, and they're going make a huge difference in the adoption and capabilities of the IoT. Unlike previous technology approaches, AI, machine learning and deep learning are based on patterns. In effect, they raise up the level of abstraction for data. An image of a cat can be megabytes of data, and a cat taken from all angles may be gigabytes of da... » read more

Hardware Security Threat Rising


Martin Scott, senior vice president and CTO of Rambus, sat down with Semiconductor Engineering to talk about an increasing problem with security, what's driving it, and why hardware is now part of the growing attack surface. What follows are excerpts of that conversation. SE: With Meltdown and Spectre, the stakes have changed because the focus is not on using hardware to get to software. It'... » read more

New 5G Hurdles


Semiconductor Engineering sat down to talk about challenges and progress in 5G with Yorgos Koutsoyannopoulos, president and CEO of Helic; Mike Fitton, senior director of strategic planning and business development at Achronix; Sarah Yost, senior product marketing manager at National Instruments; and Arvind Vel, director of product management at ANSYS. What follows are excerpts of that conversat... » read more

High-Speed SerDes At 7nm


eSilicon’s David Axelrad discusses the challenges with 56Gbps and 112Gps SerDes, and why the switch from analog to digital is required for performance and low power. https://youtu.be/E-CU8TLvjjc » read more

Pros, Cons Of ML-Specific Chips


Semiconductor Engineering sat down with Rob Aitken, an Arm fellow; Raik Brinkmann, CEO of OneSpin Solutions; Patrick Soheili, vice president of business and corporate development at eSilicon; and Chris Rowen, CEO of Babblelabs. What follows are excerpts of that conversation. To view part one, click here. Part two is here. SE: Is the industry's knowledge of machine learning keeping up with th... » read more

Will FPGAs Work As Expected?


OneSpin Solutions’ Muhammed Haque Khan, product specialist for synthesis verification, digs into equivalence checking in FPGA designs and what can go wrong with FPGA designs. https://youtu.be/RFlP2Z_-Yqs » read more

Solving Systemic Complexity


EDA and IP companies have begun branching out in entirely new directions over the past 12 to 18 months, pouring resources into entirely different problems than electrostatic issues and routing complexity. While they're still focused on solving complexity at 10/7/5nm, they also recognize that enabling Moore's Law isn't the only opportunity. For an increasing number of new and established chip... » read more

Where ML Works Best


Anirudh Devgan, president of Cadence, sat down with Semiconductor Engineering to discuss machine learning inside and outside of EDA tools and how that will affect the future of chip and system design. What follows are excerpts of that discussion. SE: How do you see the market and use of machine learning shaping up? Devgan: There are three main areas—machine learning inside, machine lear... » read more

On-Chip Monitoring Of FinFETs


Stephen Crosher, CEO of Moortec, sat down with Semiconductor Engineering to discuss on-chip monitoring and its impact on power, security and reliability, including predictive maintenance. What follows are excerpts of that conversation. SE: What new problems are you seeing in design? Crosher: There are challenges emerging for companies working on advanced nodes, including scaling and trans... » read more

← Older posts Newer posts →