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From Constraints To Tape-Out: Towards A Continuous AMS Design Flow
By Fraunhofer IIS/EAS - 12 Jun, 2019 - Comments: 0

The effort in designing analog/mixed-signal (AMS) integrated circuits is characterized by the largely manual work involved in the design of analog cells and their integration into the overall circuit. This inequality in effort between analog and digital cells increases with the use of modern, more complex technology nodes. To mitigate this problem, this paper presents four methods to improve ex... » read more

Toward Consistent Circuit-Level Aging Simulations In Different EDA Environments
By Fraunhofer IIS/EAS - 10 Apr, 2019 - Comments: 0

Aging simulations on circuit level allow integrated circuit (IC) designers to verify their circuits with respect to lifetime reliability requirements by considering the degradation of field effect transistors (FETs). To obtain significant analysis results with a reasonable effort, two prerequisites have to be fulfilled. First, reasonable models for FET degradation effects have to be set up. Sec... » read more

Ultra-Low-Power SAR ADC in 22 nm FD-SOI Technology Using Body-Biasing
By Fraunhofer IIS/EAS - 12 Dec, 2018 - Comments: 0

Today’s sensor applications show a rising demand on miniaturized autonomous sensors nodes with extreme requirements on power dissipation. One core functionality of these sensor nodes is the conversion of analog sensor signals to digital data for post processing and data communication. In this work a 11-bit Successive Approximation Register (SAR) ADC with minimized power dissipation is develop... » read more

Prediction of SRAM Reliability Under Mechanical Stress Induced by Harsh Environments
By Fraunhofer IIS/EAS - 07 Nov, 2018 - Comments: 0

On the example of a 28nm SRAM array, this work presents a novel reliability study which takes into account the effect of externally applied mechanical stress in circuit simulations. This method is able to predict the bit failures caused by the stress via the piezoresistive effect. The stability of each single SRAM cell is simulated using static noise margin. Finally, the whole array’s behavio... » read more

Temperature Reduction on a High-Power Thermal Demonstrator
By Fraunhofer IIS/EAS - 10 Oct, 2018 - Comments: 0

High-power applications in microelectronic devices and systems is a crucial and severe issue that may cause elevated thermal and thermomechanical phenomena and finally lead the fabricated system to degradation, limitation of its performance, or even failure and destruction of its features. In specific applications, such as those found in the industry and the automotive sector, the power pro... » read more

Low-Latency Image Acquisition And Processing With A Programmable Vision-System-On-Chip
By Fraunhofer IIS/EAS - 12 Sep, 2018 - Comments: 0

This work aims to demonstrate the benefits of using a Vision-System-on-Chip for image processing tasks with very high latency demands between image acquisition and processing. By leveraging a column-parallel, mixed-signal data path, which is entirely software-defined by three application-specific instruction- set processors (ASIPs), image data within multiple regions of interest can be analyzed... » read more

Dynamic Fault Injection For System-Level Simulation Of MEMS
By Fraunhofer IIS/EAS - 08 Aug, 2018 - Comments: 0

In this paper a method for dynamic fault injection and fault simulation as well as its application to MEMS based sensor systems is described. The prerequisite for this approach is the availability of accurate, but numerically efficient models for the MEMS element. Simulations based on SystemC and SystemC AMS are suitable to analyze the nominal behavior of complex sys- tems including electronics... » read more

A High-Speed Asynchronous Multi-Input Pipeline For Compaction And Transfer of Parallel SIMD Data
By Fraunhofer IIS/EAS - 16 Jul, 2018 - Comments: 0

Image sensors with programmable, highly parallel signal processing, so called Vision-Systems-on-Chip, perform computationally intensive tasks directly on the sensor itself. Therefore it is possible to limit the amount of output data to relevant image features only. Reading out such features presents a major challenge, since the position and number of features often is not known. Conventional sy... » read more

Investigation Of The Influence of Controller Types On Room Thermal Behavior – A Simulation Study
By Fraunhofer IIS/EAS - 13 Jun, 2018 - Comments: 0

To control the indoor temperature of rooms two kinds of approaches are common. The first one is to use standard PI-controllers with a set of default parameters, which often leads to insufficient performance, waste of energy and unacceptable comfort violations [Rahmati, 2003]. The other approach is to use specifically developed and adapted controllers [Seidel et al., 2015], which have the drawba... » read more

Implementation Of An Asynchronous Bundled-Data Router For A GALS NoC In The Context Of A VSoC
By Fraunhofer IIS/EAS - 09 May, 2018 - Comments: 0

Designs of asynchronous networks-on-chip are of growing interest because a complete asynchronous implemen- tation can solve the synchronization problems of large networks. However, asynchronous circuits suffer from the lack of proper design flows because their functionality often relies on timing constraints, which are not extensively supported by common CAD synthesis tools. This paper proposes... » read more

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