Author's Latest Posts


Improving Performance And Simplifying Coding With XY Memory’s Implicit Parallelism


Instruction-level Parallelism (ILP) refers to design techniques that enable more than one RISC instruction to be executed simultaneously in the same instruction, which boosts processor performance by increasing the amount of work done in a given time interval, thereby increasing the throughput. This parallelism can be explicit, where each additional instruction is explicitly part of the instruc... » read more

2021 Software Vulnerability Snapshot


The Synopsys Cybersecurity Research Center (CyRC) examined anonymized data from thousands of commercial software security tests performed by Synopsys application security testing services in 2020. The CyRC team measured this data against the 2021 OWASP Top 10 list of the most critical security risks to web applications. Key findings in the report include   97% of tests uncovered vul... » read more

Fuzz Testing Software-Defined Vehicles Using Agent Instrumentation


Cybersecurity has become intertwined into each step of the automotive development process. In particular, fuzz testing has proven to be a powerful approach to detect unknown vulnerabilities in automotive systems. But with limited instrumentation, especially on software-heavy systems such as high-performance computers (HPCs), several types of issues go undetected, including memory leaks and case... » read more

Calibrate And Configure Your Power Management IC With NVM IP


Power Management Integrated Circuits (PMICs) are the first to turn on and the last to turn off in a system. They perform the task of delivering the right voltage to component chips by regulating or boosting the voltage levels to the component chips. Some PMICs are configured once at the factory and an area-efficient OTP NVM is the best choice. When a PMIC is expected to be re-configured mult... » read more

Evolution Of Data Center Networking Technology — IP And Beyond


Ethernet is ubiquitous—it is the core technology that defines the Internet and serves to connect the world in ways that people could not imagine even one generation ago. HPC clusters are working on solving the most challenging problems facing humanity—and cloud computing is the service hosting many of the application workloads struggling with these questions. While alternative network infra... » read more

Augment Or Replace? How IAST Fits Into The AppSec Landscape


As the pace, volume, and complexity of application development continue to escalate, it becomes increasingly difficult to maintain software security and quality. More speed, more volume, and more complexity too often lead to less security and less quality. Interactive application security testing (IAST) is an exciting option for organizations looking to maintain both the speed and complexity... » read more

Accelerating Software Development With Fast Virtual Prototypes


Most of today's largest semiconductor devices are highly complex system on chip (SoC) designs, which means that they include one or more embedded processors. This indicates that software provides some of the key functionality of the chip. The system cannot be fully verified or validated without both hardware and software. However, software development generally takes more time and resources to ... » read more

Increasing IP And SoC Debug Efficiency 10X With Intelligent Waveform Reuse


Design and verification reuse lies at the very heart of every modern chip development effort. A system on chip (SoC) project with billions of gates cannot possibly be completed in reasonable time without leveraging blocks from prior projects and commercial intellectual property (IP) offerings. These reused blocks are themselves challenging to develop since they are as large and complex as previ... » read more

Flexible USB4-Based Interface IP Solution For AI At The Edge


Consumers have become accustomed to smart devices that are powered by advances in artificial intelligence (AI). To expand the devices’ total addressable market, innovative device designers build edge AI accelerators and edge AI SoCs that support multiple use cases and integration options. This white paper describes a flexible USB4-based IP solution for edge AI accelerators and SoCs. The IP so... » read more

Scaling Processor Performance And Safety To Meet Requirements For Next-Generation Safety-Critical Automotive Designs


This white paper proposes a state-of-the-art processor architecture targeting automotive safety systems that meets the requirements of such active safety systems delivering the required processing performance, providing the highest automotive safety integrity level (ASIL) while also significantly contributing to a reduction in overall cost of the systems through the use of artificial neural net... » read more

← Older posts Newer posts →