Author's Latest Posts


Anatomy Of The HDMI IP Certification Flow


HDMI IP plays a critical role in enabling HDMI 2.0 features, making 60 frames per second UHD video and audio possible in multimedia SoCs. SoC designers can avoid costly functionality and interoperability issues by selecting and integrating HDMI IP that has gone through an extensive multi-phase testing process and achieved certification. This white paper outlines the HDMI IP certification flow f... » read more

Delivering Functional Verification Engagements


With the advent of smarter and higher performing devices, there has been a tremendous increase in design complexity. Driven by new high-end hardware feature and intelligent software requirements, these devices are comprised of multi-core processors and a multitude of interface IP, memory and other analog circuitry, communicating via many different interface protocols. This poses a huge challeng... » read more

Power Hungry?


Rapid changes in SoC power issues have forced a rethinking of methodologies throughout the design flow to account for power-related effects. At 65 nanometer process nodes and below, leakage power and dynamic power consumption make it increasingly difficult to meet power budgets. Achieving timing and signal integrity closure is now tightly coupled with power optimization and power net distributi... » read more

Is Your Automotive Software Robust Enough for Hardware Faults?


In this whitepaper, we will apply virtual Fault Mode and Effect Analysis (FMEA) concepts on a specific case study, an Electrical Vehicle Powertrain (EVP) system. We will show how this EVP system is refined from a Software-in-the Loop (SIL) level to a virtual Hardware-in-the-Loop level (vHIL), using a Virtualizer Development Kit (VDK). Hardware faults are applied to the resulting system and its ... » read more

PCI Express 4.0 Controller Design And Integration Challenges


Designers need to start planning for PCI Express 4.0 integration now, because decisions for the PCIe 4.0 controller can have far-reaching consequences for the entire SoC. This paper describes the market adoption and expected use of PCIe 4.0; covers the specification; and discusses three challenges the new specification brings to controller designers. Outline Markets & Applications fo... » read more

Is Your Automotive Software Robust Enough for Hardware Faults?


A look at how virtual prototyping is expanding its reach to improve development of safety critical systems and deal with the single most complex aspect of automotive systems: the embedded software. To read more, click here. » read more

Using An Embedded Vision Processor To Build An Efficient Object Recognition System


Computer vision is a discipline that was established in the 1960s. With the advent of high-performance mobile computing platforms, we see rapid progress in computer vision capabilities. Machine vision is becoming embedded in highly integrated SoCs and expanding into emerging high-volume consumer applications such as home surveillance, games, and automotive safety. A major challenge in enabling ... » read more

Demystifying the HDCP2.2 Authentication Process


This paper explains HDCP2.2 which is the latest generation content protection protocol. Our primary focus here is to explain how the authentication process on HDCP2.2, the various steps that are necessary in able to validate the receiver. The encryption on the keys in version 2.2 is more advanced than previous versions (HDCP1.X), which basically makes it harder to break. HDCP 2.2 is required fo... » read more

Virtualizing Cloud Computing With Optimized IP For NFV SoCs


The growth in Internet traffic is impacting how cloud and carrier data center operators design their compute and data networking architectures. To meet the application demands for scale-out servers and networks, designers are implementing virtual environments such as Network Function Virtualization (NFV) to achieve higher efficiency and lower the cost and time of deploying the new applications.... » read more

Layering Protocol Verification


Layering protocols are modeled using layering structures that mirror the protocol layers. There are significant challenges in modelling verification components for layering protocols such as (1) reuse, (2) scalability, (3) controllability, and (4)observability. Furthermore, there may be requirements for complex test scenarios where a great deal of interaction is required between test sequence e... » read more

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