Author's Latest Posts

Addressing Three Critical Challenges Of USB Type-C Implementation
By Synopsys - 09 Mar, 2016 - Comments: 0

As designers are create new products and system-on-chips (SoCs) with USB Type-C support, they need to be aware of datapath and hardware/software partitioning challenges. The SoC and system design must be partitioned to support the specification’s requirements for precision analog circuitry plus high voltage/high current switches, and Type-C management software must be partitioned to execute o... » read more

Optimizing DDR Memory Subsystem Efficiency
By Synopsys - 24 Feb, 2016 - Comments: 0

The memory subsystem sits at the core of a System-on-Chip (SoC) platform and can make all the difference between a well-designed system meeting its performance requirements and a system that delivers poor performance, or even fails to operate correctly. State-of-the-art DDR memory controllers use advanced arbitration and scheduling policies to optimize DDR memory efficiency. At the same time, t... » read more

Optimizing LPDDR4 Performance And Power With Multi-Channel Architectures
By Synopsys - 10 Feb, 2016 - Comments: 0

PDDR4 offers huge bandwidth in a physically small PCB area and volume; up to 25.6 GByte/s of bandwidth at a 3,200 Mbps data rate from a single 15mmx15mm LPDDR4 package when two dies are packaged together. LPDDR4 builds on the success of LPDDR2 and LPDDR3 by adding new features and introducing a major architectural change. This white paper explains how LPDDR4 is different from all previous JEDEC... » read more

IC Compiler II Multi-Level Physical Hierarchy Floorplanning
By Synopsys - 27 Jan, 2016 - Comments: 0

Large, complex SoC designs require hierarchical layout methodologies that span multiple levels of physical hierarchy. Many EDA tools only handle two levels of physical hierarchy at a given time resulting in longer layout schedules that are risky at best. Synopsys' IC Compiler II provides automation designs with multiple levels of hierarchy that minimizes time to results, provides best QoR, and ... » read more

True Random Number Generators For Truly Secure Systems
By Synopsys - 13 Jan, 2016 - Comments: 0

Random numbers form the basis, or root, of most security systems. Yet the methods for generating random numbers vary widely in practice as well as efficacy. Over time, many popular randomization algorithms and circuit implementations have been shown to be provably flawed. The paper will examine current methods for generating random numbers based on various sources of entropy as well as their as... » read more

Scaling Automated Software Testing With Virtualizer Development Kits
By Synopsys - 21 Dec, 2015 - Comments: 0

In this whitepaper we will discuss how simulation-based Virtualizer Development Kits (VDKs) enable software to be tested in a system context much earlier, bridging the gap with unit and integration testing. Moreover, we will discuss how VDKs offer a more scalable solution as they consist of simulation models and hence alleviate the dependency on hardware labs. To read more, click here. » read more

Safety in SoCs
By Synopsys - 09 Dec, 2015 - Comments: 0

Today’s system-on-chip (SoC) designs are becoming more complex, increasing the pressure on verification and design teams to deliver fully functional designs. Recent studies have shown that over 50% of the development time on a complex IC is now being spent on verification, revealing the severity of the problem project teams are facing. As more SoC designs are used in electronic systems deploy... » read more

Software is Eating the World
By Synopsys - 23 Nov, 2015 - Comments: 0

The statement "software is eating the world" was coined by internet pioneer Marc Andreessen in 2011. Over the last decade, the role of electronics in our daily life has changed dramatically. To read more, click here. » read more

Design, Test & Repair Methodology For FinFET-Based Memories
By Synopsys - 11 Nov, 2015 - Comments: 0

Like any IP block, memories need to be tested. But unlike many other IP blocks, memory test is not as simple as pass/fail. The advent of FinFET-based memories presents new memory test challenges. This white paper covers: The new design complexities, defect coverage and yield challenges presented by FinFET-based memories. How to synthesize test algorithms for detection and diagnosis of Fin... » read more

FinFET Technology
By Synopsys - 23 Sep, 2015 - Comments: 0

This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with Synopsys, one of their ecosystem partners, to deliver a complete solution. Key elements of this solution include comprehensive FinFET profiling without impact to design tool runtime and proven, verified IP availability. The TSMC 16-nm FinFET solution will ensure mutual customers swiftly move to... » read more

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