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3D Printing To Create Spatially Freeform, Nanomaterial-based Electronics (Rice, U. of Utah, NUS)
By Technical Paper Link - 09 Feb, 2026 - Comments: 0

Researchers from Rice University, University of Utah and National University of Singapore (NUS) published "Three-dimensional printing of nanomaterials-based electronics with a metamaterial-inspired near-field electromagnetic structure." Abstract "Three-dimensional (3D) printing can create freeform architectures and electronics with unprecedented versatility. However, the full potential of... » read more

Rutile TiO2 As A Post-ZrO2 Dielectric Platform for Next-Gen DRAM Capacitors (KIST)
By Technical Paper Link - 07 Feb, 2026 - Comments: 0

Researchers at Korea Institute of Science and Technology (KIST) published "Beyond ZrO2: Rutile TiO2 as the Dielectric Platform for Next-Generation DRAM Capacitors." Abstract "As DRAM technology nodes move into the sub-10 nm regime, capacitor scaling is increasingly constrained by both footprint loss and a hard physical thickness limit for the entire electrode–dielectric–electrode stac... » read more

Thermal Characterization For Power Semiconductor Packages (KATECH)
By Technical Paper Link - 06 Feb, 2026 - Comments: 0

Researchers from Korea Automotive Technology Institute published "Analytical Extraction of Thermal Resistance in Power Semiconductors Using Structural Function Derivatives and Series Resistance Modeling." Abstract "Junction-to-case thermal resistance (RthJC ) is a critical parameter for assessing the reliability and thermal performance of power semiconductor devices. Conventional JEDEC-ba... » read more

Overview of Interface Dipole Engineering: Formation Mechanisms, Control Methods, And Emerging Applications (SNU, Sejong U.)
By Technical Paper Link - 06 Feb, 2026 - Comments: 0

Researchers at Seoul National University and Sejong University published "Interface dipole modulation for gate dielectrics in Field-Effect transistors: a review." Abstract "Interface dipole engineering has recently become a key technology in the fabrication of semiconductor FETs. This review comprehensively covers the principles, methods, and applications of interface dipoles in gate diel... » read more

Comprehensive System-Level Performance Model For p-SRAM-Based IMC (USC, UW-Madison)
By Technical Paper Link - 06 Feb, 2026 - Comments: 0

Researchers at USC and University of Wisconsin-Madison published "System-Level Performance Modeling of Photonic In-Memory Computing." Abstract "Photonic in-memory computing is a high-speed, low-energy alternative to traditional transistor-based digital computing that utilizes high photonic operating frequencies and bandwidths. In this work, we develop a comprehensive system-level performa... » read more

300mm Fab-Compatible Integration Flow for Planar 2D FETs (imec, KU Leuven)
By Technical Paper Link - 04 Feb, 2026 - Comments: 0

Imec and KU Leuven researchers published "Integration and electrical evaluation of WS2 and MoS2 fets in a 300 mm pilot line." Abstract "2D materials have the potential to extend and augment the CMOS scaling roadmap. However, upscaling from lab-based demonstrators to 300 mm-compatible integration modules presents unique challenges. In this work, we address these challenges through ... » read more

A Manufacturing Approach That Brings Diamond Quantum Photonics Closer To Industrial Production (MIT, KAUST et al.)
By Technical Paper Link - 02 Feb, 2026 - Comments: 0

"Foundry-Enabled Patterning of Diamond Quantum Microchiplets for Scalable Quantum Photonics" was published by researchers at MIT, KAUST, PhotonFoundries and MITRE. Abstract "Quantum technologies promise secure communication networks and powerful new forms of information processing, but building these systems at scale remains a major challenge. Diamond is an especially attractive material fo... » read more

ML for Energy-Performance-Aware Scheduling On Heterogeneous Multicore Architectures (Cambridge)
By Technical Paper Link - 02 Feb, 2026 - Comments: 0

University of Cambridge researchers published "Machine Learning for Energy-Performance-aware Scheduling." Abstract "In the post-Dennard era, optimizing embedded systems requires navigating complex trade-offs between energy efficiency and latency. Traditional heuristic tuning is often inefficient in such high-dimensional, non-smooth landscapes. In this work, we propose a Bayesian Optimizatio... » read more

HW-Triggered Backdoors Across Common GPU Accelerators (BIFOLD, TU Berlin, CISPA)
By Technical Paper Link - 02 Feb, 2026 - Comments: 0

A new technical paper titled "Hardware-Triggered Backdoors" was published by researchers at Berlin Institute for the Foundations of Learning and Data (BIFOLD), TU Berlin and CISPA Helmholtz Center for Information Security. Abstract "Machine learning models are routinely deployed on a wide range of computing hardware. Although such hardware is typically expected to produce identical result... » read more

Benchmark For AI-Aided Chip Design That Evaluates LLMs Across 3 Critical Tasks (UCSD, Columbia)
By Technical Paper Link - 30 Jan, 2026 - Comments: 0

Researchers at UCSD and Columbia University published "ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design." Abstract "While Large Language Models (LLMs) show significant potential in hardware engineering, current benchmarks suffer from saturation and limited task diversity, failing to reflect LLMs' performance in real industrial workflows. To address t... » read more

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