Complex Mix Of Processors At The Edge


With AI changing so fast, it’s a juggle for companies to ensure they can deliver the best performance now while also future-proofing for unknown AI models or a completely different approach to training and inference that may emerge. There are a slew of options for high-end and budget phones, hyperscalers, and low-cost, low-power edge devices, and while GPUs keep making headlines, many designe... » read more

Server-Scale Programmable Photonic Fabric to Interconnect Accelerators Within Servers (Cornell University, Lightmatter)


A new technical paper titled "Morphlux: Programmable chip-to-chip photonic fabrics in multi-accelerator servers for ML" was published by researchers at Cornell University and Lightmatter. Abstract "We optically interconnect accelerator chips (e.g., GPUs, TPUs) within compute servers using newly viable programmable chip-to-chip photonic fabrics. In contrast, today, commercial multi-accelerat... » read more

Energy-Efficient Signal Detectors For Massive MIMO Using SRAM-Based IMCs (Univ. of Illinois at Urbana–Champaign)


A new technical paper titled "Energy-Accuracy Trade-Offs in Massive MIMO Signal Detection Using SRAM-Based In-Memory Computing" was published by researchers at the University of Illinois at Urbana–Champaign. Abstract "This paper investigates the use of SRAM-based in-memory computing (IMC) architectures for designing energy efficient and accurate signal detectors for massive multi-input mu... » read more

Microservice-Based LLM Agents Enable EDA Flow Automation (Duke Univ. and Univ. of Maryland)


A new technical paper titled "AutoEDA: Enabling EDA Flow Automation through Microservice-Based LLM Agents" was published by researchers at Duke University and University of Maryland. Abstract "Modern Electronic Design Automation (EDA) workflows, especially the RTL-to-GDSII flow, require heavily manual scripting and demonstrate a multitude of tool-specific interactions which limits scalabili... » read more

Power Gating Enabling in NPUs (Univ. of Illinois Urbana-Champaign)


A new technical paper titled "ReGate: Enabling Power Gating in Neural Processing Units" was published by researchers at the University of Illinois Urbana-Champaign. Abstract "The energy efficiency of neural processing units (NPU) is playing a critical role in developing sustainable data centers. Our study with different generations of NPU chips reveals that 30%–72% of their energy consump... » read more

The Severity Of Test Escapes And SDCs Caused By Them (Google)


A new technical paper titled "Silent Data Corruption by 10x Test Escapes Threatens Reliable Computing" was published by Google. Abstract "Too many defective compute chips are escaping existing manufacturing tests -- at least an order of magnitude more than industrial targets across all compute chip types in data centers. Silent data corruptions (SDCs) caused by test escapes, when left unadd... » read more

AI, From A To Z


First in a seven-part series: What's the difference between AI, ML, DL, LLMs, and agentic AI? Is it truly revolutionary, or is it an evolutionary series of steps that have enabled machines to do much more than in the past? Jon Herlocker, vice president and general manager of software analytics at Cohu, talks about the evolution of AI over nearly 70 years, the chain of innovation that has enable... » read more

Chip Industry Week in Review


Lines are blurring between government and industry: On the heels of last week's resignation demand, Intel CEO Lip-Bu Tan met with President Trump on Monday, with the President later saying, "The meeting was a very interesting one. His success and rise is an amazing story."  Now, Bloomberg reports the Trump administration is in talks with Intel for the U.S. government to take a stake in th... » read more

System-Level Design For 1.6 Tbps Interoperability In AI Data Centers


By Madhumita Sanyal and Diwakar Kumaraswamy The rapid escalation of AI/ML workloads—driven by increasingly large language models—is reshaping high-performance computing and AI data center architectures. Real-time inference and large-scale training are pushing the limits of compute and interconnect performance. With model sizes and parameter counts doubling every 4–6 months, infrastruct... » read more

Re-Architecting AI For Power


The industry is becoming increasingly concerned about the amount of power being consumed by AI, but there is no simple solution to the problem. It requires a deep understanding of the application, the software and hardware architectures at both the semiconductor and system levels, and how all of this is designed and implemented. Each piece plays a role in the total power consumed and the utilit... » read more

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