Transferable Hybrid Bonding Technique That Allows For High Integration Density In Advanced Packaging

By Brewer Science - 21 Aug, 2025 - Comments: 0

A technical paper titled "Hierarchical Multi-Layer and Stacking Vias with Novel Structure by Transferrable Cu/Polymer Hybrid Bonding for High Speed Digital Applications" was published by researchers at Industrial Technology Research Institute (ITRI) and Brewer Science. The paper demonstrates a "novel structure with hierarchical multi-layer stacking vias as well as transferred hybrid bonding,... » read more

Overview: Ultra Ethernet’s Design and Architectural Advancements (ETH Zurich, Broadcom, HPE et al.)

By Technical Paper Link - 20 Aug, 2025 - Comments: 0

A new technical paper titled "Ultra Ethernet's Design Principles and Architectural Innovations" was published by researchers at ETH Zurich, Broadcom, Hewlett Packard Enterprise, OpenAI, Intel, Microsoft, AMD and Cisco. Abstract "The recently released Ultra Ethernet (UE) 1.0 specification defines a transformative High-Performance Ethernet standard for future Artificial Intelligence (AI) and ... » read more

Blog Review: August 20

By Jesse Allen - 20 Aug, 2025 - Comments: 0

Cadence's Sriram Sharma Kalluri finds that time-of-flight sensors are poised to revolutionize ADAS by generating precise 3D point clouds that, particularly when combined with lidar, contribute to an exceptionally accurate and comprehensive understanding of the vehicle's surroundings. Synopsys' Igor Markov and other industry experts discuss how quantum computing is moving from research to p... » read more

Best Options For Using AI In Chip Design

By Ed Sperling - 20 Aug, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss how and where AI can be applied to chip design to maximize its value, and how that will impact the design process, with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at S... » read more

Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes with High Core Density (Politecnico di Torino, imec et al.)

By Technical Paper Link - 19 Aug, 2025 - Comments: 0

A new technical paper titled "Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes" was published by researchers at Politecnico di Torino, EPFL, National Technical University of Athens and imec. Abstract "This paper presents the physical design exploration of a domain-specific processor (DSIP) architecture targeted at machine learning (ML), address... » read more

Thermally-Aware, Multi-Objective Scheduling Framework for DL Workloads on Heterogeneous Multi-Chiplet PIM Architectures (UW–Madison, Washington State)

By Technical Paper Link - 19 Aug, 2025 - Comments: 0

A new technical paper titled "THERMOS: Thermally-Aware Multi-Objective Scheduling of AI Workloads on Heterogeneous Multi-Chiplet PIM Architectures" was published by researchers at the University of Wisconsin–Madison and Washington State University. Abstract "Chiplet-based integration enables large-scale systems that combine diverse technologies, enabling higher yield, lower costs, and sca... » read more

Scheduling Architecture Integrated With M3D BEOL Memories For LLM Inference (Georgia Tech, Samsung)

By Technical Paper Link - 19 Aug, 2025 - Comments: 0

A new technical paper titled "Architecting Long-Context LLM Acceleration with Packing-Prefetch Scheduler and Ultra-Large Capacity On-Chip Memories" was published by researchers at Georgia Institute of Technology and Samsung. Abstract "Long-context Large Language Model (LLM) inference faces increasing compute bottlenecks as attention calculations scale with context length, primarily due to t... » read more

Launching The Full Potential Of 3D IC With Front-End Architectural Planning

By Siemens EDA - 19 Aug, 2025 - Comments: 0

3D IC and chiplet-based design have the potential to accelerate the pace of semiconductor industry innovation. 3D IC design teams pack more functionality closer together and achieve higher levels of systems integration and performance in a smaller footprint faster than what’s possible with traditional SoC implementation. To achieve the full potential of 3D IC, teams need cost-effective fro... » read more

Research Bits: August 19

By Jesse Allen - 19 Aug, 2025 - Comments: 0

Co-packaged optics Researchers from the Massachusetts Institute of Technology (MIT) and Bridgewater State University developed a new way to co-package photonic and electronic chips that uses existing automated pick-and-place assembly equipment in traditional fabs along with a less-expensive passive alignment process. “We’ve developed a packaging design [for integrating photonics with el... » read more

Chip Industry Technical Paper Roundup: August 19

By Emma Riverso - 19 Aug, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=465 /] Find more semiconductor research papers here. » read more

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