Machine Learning In Semiconductor Manufacturing


Second in a seven-part series: Machine learning is a mathematical construct that is the foundation for nearly all the advancements in AI. ML came first, but it remains relevant even today. It can be applied to semiconductor fab for such things as predictive maintenance of manufacturing equipment, rather than just maintenance on a schedule, which decreases downtime. But getting this right is har... » read more

Chip Industry Week In Review


The EU’s tariffs on semiconductors will not exceed 15%, according to Trump’s latest trade deal. In addition, the EU committed to purchasing at least $40 billion worth of U.S. AI chips as well as other investments. [FAQ is here.] Lifelines for Intel: Intel inked a deal to sell the U.S. government a 10% non-voting equity stake in its business, worth $8.9 billion. The stake will be fun... » read more

Why 3D NAND Layers Bend (And How To Prevent It)


3D NAND flash memory is built by vertically stacking multiple alternating layers (tiers) of silicon nitride (SiN) and oxide (TEOS) on top of each other. A major challenge in producing multilayered 3D NAND devices is tier bending and tier collapse. These undesirable conditions can be caused by a combination of factors. Using the virtual Design of Experiment (DOE) capabilities in SEMulator... » read more

Materials Modeling Of Superconducting Qubits In Quantum Computers


While the concept of quantum computing has been discussed for more than 40 years, only recently have experiments indicated that a practical quantum computer may be possible. Recent developments in this area have captured headlines with dramatic claims—and equally dramatic rebuttals. Google’s Willow chip demonstrated error-corrected operations in late 2024, while D-Wave’s assertion of quan... » read more

Manufacturing At The Limits


Hybrid bonding has been in production for several years, with mature flows capable of delivering robust yields using 10µm interconnects. At that scale, processes can tolerate hundreds of nanometers of overlay variation, modest differences in wafer bow, and particle sizes rivaling the interconnect height without catastrophic impact. Hybrid bonding is compatible with optical metrology, existing ... » read more

How Guardbanding Of Inline Wafer Defects Can Improve Chip Reliability Insurance


Partially defective, marginal die can still be functional enough to pass final electrical test. Some of these “walking wounded” chips get past final testing, but in the customer's end product, under ongoing stress, they may fail. This is a particularly serious issue with automotive, medical and other customers who demand maximum long-term device reliability. The semiconductor industry ha... » read more

Reticle Stitching Bumps Up Silicon Interposer Costs


Advanced packaging often relies on silicon interposers to connect chiplets and other components inside a package. The problem is that interposers typically exceed the reticle limit, which adds both complexity and cost. An interposer is essential for 2.5D and 3.5D architectures. As device scaling runs out of steam, chipmakers are decomposing planar SoCs into chiplets and connecting them throu... » read more

2024 UMC Sustainability Report


Message from UMC's ESG Steering Committee Chairman: Jason Wang and Shan-Chieh Chien, Co-presidents and ESG Steering Committee Chairmen. "While the global economy gradually recovered from the pandemic, 2024 presented different challenges, including geopolitical shifts, inflation, inventory adjustments, and industry overcapacity. Despite these headwinds, our management team demonstrated strong... » read more

From Latency To Reaction: Simulating The Next Wafer Demand Inflection


The semiconductor industry faces an unprecedented paradox: AI demand is booming, fab investments are rising, yet wafer shipments remain stubbornly flat. What's driving this disconnect, and when will it break? As of mid-2025, the global silicon wafer market appears calm on the surface, but underlying structural tensions are quietly mounting. The demand for AI semiconductors remains resilient,... » read more

The End Of Copper Interconnects?


After nearly three decades, the era of copper interconnects may be coming to an end. Sort of. At interconnect CDs below 10nm, copper is no longer the best metallization choice. Yet it remains unsurpassed for larger features. The most serious challenge to continued copper scaling is the metal’s dramatic increase in resistivity at dimensions below its relatively large (40nm) mean free path l... » read more

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