Making SoC Integration Simple – Achieve Higher Productivity and Quality


The development of large-scale semiconductors has never been a simple task, but with the development of ever more powerful computers, software environments, and verification models, the task of designing cutting-edge chips becomes far more manageable. However, now that many chips being developed are utilizing as many as 1000 IP cores, the challenges of correctly connecting these modules togethe... » read more

A Comparative Study With Horizontal and Verticals FETs (POSTECH, Georgia Tech)


A new technical paper titled "Vertical FET Optimization at Angstrom Nodes: A Comparative Study With Horizontal FET" was published by researchers at POSTECH and Georgia Institute of Technology. Abstract "For the first time, this study presents two novel vertical FET (VFET) structures and conducts a quantitative analysis to assess the competitiveness of VFET in comparison to two types of hori... » read more

An LLM-based Agentic Framework For Photonic IC Design Automation (U. of Toronto, Max Planck, MIT Et Al.)


A new technical paper titled "AI Agents for Photonic Integrated Circuit Design Automation" was published by researchers at the University of Toronto, Max Planck Institute of Microstructure Physics, GDSFactory, MIT and Axiomatic_AI Inc. Abstract "We present Photonics Intelligent Design and Optimization (PhIDO), a multi-agent framework that converts natural-language photonic integrated circui... » read more

Advanced Part Average Testing For Chips


Part average testing, one of the mainstays of semiconductor test, is becoming much more challenging at advanced nodes and in multi-die assemblies. In the past, PAT produced a Gaussian distribution that made it relatively simple to find outliers. That's no longer the case. Advanced packaging and leading-edge designs have unique attributes that determine which rules apply, such as the thickness o... » read more

Hardware Technologies And Algorithms for Vector Symbolic Architectures (Purdue Univ., Georgia Tech)


A new technical paper titled "Cross-Layer Design of Vector-Symbolic Computing: Bridging Cognition and Brain-Inspired Hardware Acceleration" was published by researchers at Purdue University and Georgia Institute of Technology. Abstract "Vector Symbolic Architectures (VSAs) have been widely deployed in various cognitive applications due to their simple and efficient operations. The widesprea... » read more

Chip Industry Technical Paper Roundup: August 26


New technical papers recently added to Semiconductor Engineering’s library: [table id=467 /] Find more semiconductor research papers here. » read more

Research Bits: August 26


THz-optical converter Researchers from École Polytechnique Fédérale de Lausanne (EPFL) and Harvard University designed a chip that can convert between electromagnetic pulses in the terahertz and optical ranges on the same device. Applications include communication, sensing, spectroscopy, and computing. The design embeds micron-sized transmission lines into a lithium niobate photonic chip... » read more

Reconfigurable Single-Walled CNT FeFET (Univ. of Pennsylvania, Yonsei et al.)


A new technical paper titled "Reconfigurable single-walled carbon nanotube ferroelectric field-effect transistors" was published by researchers at University of Pennsylvania, Yonsei University, Kookmin University, SKKU and Peking University. Abstract "Reconfigurable devices have garnered significant attention for alleviating the scaling requirements of conventional complementary metal-oxide... » read more

Nanofabrication Protocol That Allows Patterning Metallic Electrodes on 2D Materials Reliably (KAUST, National University of Singapore)


A new technical paper titled "High-yield photolithography protocol to pattern metallic electrodes on 2D materials without adhesive metallic layers" was published by researchers at KAUST and National University of Singapore. Abstract "When using two-dimensional (2D) materials to build electronic devices, adjacent metallic films need to be deposited to form electrodes. However, weak adhesion ... » read more

How Semiconductor Fabs Use Water


Water — lots of it — is a critical enabler for advanced chip architectures, lithography, and back-end packaging. It feeds the ultra-pure water loops that touch every wafer, sluicing heat out of tools that run hotter at each node, and carrying spent chemistries to treatment. The natural reaction to reports that fabs “use millions of gallons of water” is concern, but the engineering re... » read more

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