Research Bits: May 20


Smart t-shirt with sound waves Researchers at ETH Zurich developed a smart textile that uses acoustic waves passed through glass fibers to measure touch, pressure, and movement. The researchers said that using acoustic waves rather than electronics makes measurements more precise with low power consumption and the textiles lighter, more breathable, and easier to wash. It also uses readily avai... » read more

More Data, More Redundant Interconnects


The proliferation of AI dramatically increases the amount of data that needs to be processed, stored, and moved, accelerating the aging of signal paths through which that data travels and forcing chipmakers to build more redundancy into the interconnects. In the past, nearly all redundant data paths were contained within a planar chip using a relatively thick silicon substrate. But as chipma... » read more

Cache Side-Channel Attacks On LLMs (MITRE, WPI)


A new technical paper titled "Spill The Beans: Exploiting CPU Cache Side-Channels to Leak Tokens from Large Language Models" was published by researchers at MITRE and Worcester Polytechnic Institute. Abstract "Side-channel attacks on shared hardware resources increasingly threaten confidentiality, especially with the rise of Large Language Models (LLMs). In this work, we introduce Spill The... » read more

Demonstration Of EUV Scatterometry On A 2D Periodic Interconnect


A new technical paper titled "Coherent EUV scatterometry of 2D periodic structure profiles with mathematically optimal experimental design" was published by researchers at University of Colorado, NIST, Samsung and KMLAbs. Abstract "Extreme ultraviolet (EUV) scatterometry is an increasingly important metrology that can measure critical parameters of periodic nanostructured materials in a fas... » read more

Customizing A LLM Model For VHDL Design of High-Performance MPUs (IBM)


A new technical paper titled "Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors" was published by researchers at IBM. Abstract "The use of Large Language Models (LLMs) in hardware design has taken off in recent years, principally through its incorporation in tools that increase chip designer productivity. There has been considerable discussion about the ... » read more

Chip Industry Week in Review


Check out the Inside Chips podcast for our behind-the-scenes analysis. Newly proposed U.S. legislation called the Chip Security Act would use location verification tracking as a tool to help combat chip smuggling. This follows a report by the Economist that showed Taiwan exports of advanced chips to Malaysia in the first quarter has nearly reached 2024 totals, heightening concerns that China... » read more

Intent Meets Implementation


Power efficiency has become a must-have in today’s ASIC and SoC designs. It’s no longer just about squeezing out more performance. It’s about doing so without draining the battery, wasting energy or overheating the system. Whether the chip is headed for a smartphone, a server rack in an AI datacenter or the control system of an autonomous vehicle, managing power wisely is as critical as m... » read more

Optimizing Analog With Layout In The Loop


Meeting high-performance requirements at low power isn’t easy. What is already challenging in digital is even more complex in analog. After specification and block-level system concept, the analog design flow typically spends considerable time coming up with well-working schematic-level topologies. However, once layout parasitics become apparent through parasitic extraction, the seemingly opt... » read more

Best Practices For Power-Aware Verification: Because Designing For Low Power Is Only Half The Battle


As modern chips push the limits of power efficiency, power management has become a top priority. With today’s increasingly complex devices, verifying power intent isn’t just a technical requirement. It’s a necessity for building reliable silicon. One of the most important lessons learned in recent years is that RTL and power intent must evolve together. Treating power intent as a post... » read more

HBM4 Elevates AI Training Performance To New Heights


Generative and Agentic AI are pushing an extremely rapid evolution of computing technology. With leading-edge LLMs now in excess of a trillion parameters, training takes an enormous amount of computing capacity, and state-of-the-art training clusters can employ more than 100,000 GPUs. High Bandwidth Memory (HBM) provides the vast memory bandwidth and capacity needed for these demanding AI train... » read more

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