Scalable Approach For Fabricating Sub-10nm Nanogaps


A new technical paper titled "A progressive wafer scale approach for Sub-10 nm nanogap structures" was published by researchers at Seoul National University, Chung-Ang University, Mohammed VI Polytechnic University and Ulsan National Institute of Science and Technology. "We have advanced the atomic layer lithography method into an efficient, scalable approach for fabricating sub-10 nm nanoga... » read more

Research Bits: Apr. 7


DNA scaffolds for 3D electronics Researchers from Columbia University, Brookhaven National Laboratory, and University of Minnesota used DNA to help create self-assembled 3D electronic devices with nanometer-size features. The team deposited arrays of gold squares on a surface, onto which they could attach short pieces of DNA. These served as anchors to which they could fasten eight-sided di... » read more

Chip Industry Technical Paper Roundup: Apr. 7


New technical papers recently added to Semiconductor Engineering’s library: [table id=419 /] Find more semiconductor research papers here. » read more

2030 Data Center AI Chip Winners: The Trillion Dollar Club


At the start of 2025, I believed AI was overhyped, ASICs were a niche, and a market pullback was inevitable. My long-term view has changed dramatically. AI technology and adoption is accelerating at an astonishing pace. One of the GenAI/LLM leaders, or Nvidia, will be the first $10 Trillion market cap company by 2030. Large language models (LLMs) are rapidly improving in both capability and ... » read more

Side-by-Side Benchmark of NPU Platforms (Imperial College London, Cambridge)


A new technical paper titled "Benchmarking Ultra-Low-Power μNPUs" was published by researchers at Imperial College London and University of Cambridge. Abstract "Efficient on-device neural network (NN) inference has various advantages over cloud-based processing, including predictable latency, enhanced privacy, greater reliability, and reduced operating costs for vendors. This has sparked t... » read more

Study Of Multi-Die And Multi-Technology Floorplanning (Texas A&M, Duke)


A new technical paper titled "PPAC Driven Multi-die and Multi-technology Floorplanning" was published by Texas A&M University and Duke University. Abstract "In heterogeneous integration, where different dies may utilize distinct technologies, floorplanning across multiple dies inherently requires simultaneous technology selection. This work presents the first systematic study of multi-die ... » read more

Emerging Cybersecurity Risks in Connected Vehicles, With Focus On In-Vehicle and Vehicle-Edge Platforms


A new technical paper titled "Security Risks and Designs in the Connected Vehicle Ecosystem: In-Vehicle and Edge Platforms" was published by researchers at Università di Pisa, Ford Motor Company, MIT, and the Institute of Informatics and Telematics (Pisa). Abstract "The evolution of Connected Vehicles (CVs) has introduced significant advancements in both in-vehicle and vehicle-edge platfor... » read more

Thermal Slip Length at a L/S Interface: Power Law Relations From Spatial and Frequency Attributes of the Contact Layer (Caltech)


A new technical paper titled "Thermal Slip Length at a Liquid/Solid Interface: Power Law Relations From Spatial and Frequency Attributes of the Contact Layer" was published by researchers at California Institute of Technology, , T. J. Watson Sr. Laboratories of Applied Physics. Abstract "Specialty integrated chips for power intensive tasks like artificial intelligence generate so much heat ... » read more

Photonic-SRAM Bitcell for High-Speed On-Chip Photonic Memory and Compute Systems (UW, USC, GF)


A new technical paper titled "Design of Energy-Efficient Cross-coupled Differential Photonic-SRAM (pSRAM) Bitcell for High-Speed On-Chip Photonic Memory and Compute Systems" was published by researchers at University of Wisconsin–Madison, USC and GlobalFoundries. Abstract "In this work, we propose a novel differential photonic static random access memory (pSRAM) bitcell design using fabri... » read more

Adaptive RISC-V Cache Architecture for Near-Memory Extensions (Politecnico di Torino, EPFL)


A new technical paper titled "ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions" was published by researchers at Politecnico di Torino and EPFL. Abstract "Modern data-driven applications expose limitations of von Neumann architectures - extensive data movement, low throughput, and poor energy efficiency. Accelerators improve performance but lack flexibility and require... » read more

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