Material Properties of Si/SiGe Multi-layer Stacks For CFETs (Imec, Ghent U, et al.)


A new technical paper titled "Epitaxial Si/SiGe Multi-Stacks: From Stacked Nano-Sheet to Fork-Sheet and CFET Devices" was published by researchers at Imec and Ghent University, et al. Abstract "After a short description of the evolution of metal-oxide-semiconductor device architectures and the corresponding requirements on epitaxial growth processes, the manuscript describes the material pr... » read more

CFETs with Optimized Buried Power Rails


A technical paper titled "Buried power rail to suppress substrate leakage in complementary field effect transistor (CFET)" was published by researchers at Korea University and Sungkyunkwan University. Abstract "In the pursuit of minimizing the track height in standard cell, a design innovation incorporating complementary field-effect transistors (CFETs) and Buried Power Rail (BPR) technolog... » read more

Low-Temperature Solid-Liquid Interdiffusion Bonding For High-Density Interconnect Applications


A new technical paper titled "Facilitating Small-Pitch Interconnects with Low-Temperature Solid-Liquid Interdiffusion Bonding" was published by researchers at Aalto University in Finland. Abstract "The trend for 3D heterogeneous integration drives the need for a low-temperature bonding process for high-density interconnects (HDI). The Cu-Sn-In based solid-liquid interdiffusion (SLID) is a p... » read more

Temporal Variation in DRAM Read Disturbance in DDR4 and HBM2 (ETH Zurich, Rutgers)


A new technical paper titled "Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance" was published by researchers at ETH Zurich and Rutgers University. Abstract "Modern DRAM chips are subject to read disturbance errors. State-of-the-art read disturbance mitigations rely on accurate and exhaustive characterization of the read disturbance threshold... » read more

Blog Review: Feb. 19


Cadence's Ravi Vora explains the AMBA Local Translation Interface protocol, which defines the point-to-point protocol between an I/O device and the Translation Buffer Unit of an Arm System Memory Management Unit. Siemens' Stephen V. Chavez provides a checklist for ensuring the quality and functionality of a PCB at every stage, from design through fabrication, assembly, and testing, with a fo... » read more

What’s Next In Advanced Packaging?


Experts at the Table: Semiconductor Engineering sat down to discuss 3D-IC progress and issues, photonics, and tradeoffs with different interposers and bridge technologies, with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What fo... » read more

HW-Aligned Sparse Attention Architecture For Efficient Long-Context Modeling (DeepSeek et al.)


A new technical paper titled "Native Sparse Attention: Hardware-Aligned and Natively Trainable Sparse Attention" was published by DeepSeek, Peking University and University of Washington. Abstract "Long-context modeling is crucial for next-generation language models, yet the high computational cost of standard attention mechanisms poses significant computational challenges. Sparse attention... » read more

Research Bits: Feb. 18


Predicting band gap with neural networks Researchers from Kyoto University developed a machine learning model to predict the band gap of novel semiconductor materials. Using data from almost 2,000 semiconductor materials, the team tested six different neural networks. They found that the incorporation of conditional generative adversarial networks (CGAN) and message passing neural networks ... » read more

Chip Industry Technical Paper Roundup: Feb. 18


New technical papers recently added to Semiconductor Engineering’s library: [table id=406 /] Find all technical papers here. » read more

Modeling and Simulation of NVM Technologies: Tutorial (TU Dormand, TU Dresden, KIT, FAU)


A new technical paper titled "Modeling and Simulating Emerging Memory Technologies: A Tutorial" was published by researchers at TU Dortmund, TU Dresden, Karlsruhe Institute of Technology (KIT) and FAU ErlangenNürnberg. "This tutorial presents a simulation toolchain through four detailed case studies, showcasing its applicability to various domains of system design, including hybrid main-mem... » read more

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