Using AI To Glue Disparate IC Ecosystem Data
By Ed Sperling and Ann Mutschler - 26 Sep, 2024 - Comments: 0

AI holds the potential to change how companies interact throughout the global semiconductor ecosystem, gluing together different data types and processes that can be shared between companies that in the past had little or no direct connections. Chipmakers always have used abstraction layers to see the bigger picture of how the various components of a chip go together, allowing them to pinpoi... » read more

Managing Performance in Modern SoC Designs
By John Min - 26 Sep, 2024 - Comments: 0

As industries like automotive, consumer electronics, telecommunications and artificial intelligence (AI) push for greater processing power, efficiency and scalability, system-on-chip (SoC) designs have rapidly evolved to meet these demands. With the growing complexity of modern SoCs, designers face the challenge of managing an increasing number of interconnected IP blocks while ensuring seamles... » read more

DDR5 UDIMM Evolution To Clock Buffered DIMMs (CUDIMM)
By Shyam Sharma - 26 Sep, 2024 - Comments: 0

DDR5 is the latest generation of PCDDR memory that is used in a wide range of application like data centers, Laptops and personal computers, autonomous driving systems, servers, cloud computing, and gaming are now increasingly being used for AI applications with advances in memory bandwidth and density to allow DDR5 DIMMs (Dual Inline Memory Modules) to support densities higher then 256 GB per ... » read more

RAG-Enabled AI Stops Hallucinations, Adds Sources
By Karen Heyman - 26 Sep, 2024 - Comments: 0

Many EDA companies have taken the first steps to incorporate generative AI into their tools, and in such tightly controlled environments GenAI appears to have great benefits. But its broader adoption has been delayed by its notorious inaccuracy, giving results that are often out of date, untrue, and unsourced. That's starting to change. GenAI is evolving so rapidly that these kinds of proble... » read more

Signal Integrity Basics
By Siemens EDA - 26 Sep, 2024 - Comments: 0

In this orientation to signal integrity basics, we aim to introduce several important and fundamental concepts of signal integrity for the beginner. Most explanations are provided at a high level without a lot of depth and math, and examples are provided with a focus on comparison rather than detailed numerical results. Of course, background depth, math, and numerical details are very important... » read more

Pressure Builds To Adopt Virtual Prototypes
By Brian Bailey - 26 Sep, 2024 - Comments: 0

Virtual prototypes, often used as a niche tool in the past, are becoming essential for developing complex systems. In fact, systems companies are finding they no longer can function without them. In the semiconductor industry, a virtual prototype is a model for a system at an abstraction level above RTL. But there is no such thing as 'the' virtual prototype. They are constructed for a partic... » read more

Method To Determine The Permittivity of Dielectric Materials in 3D Integrated Structures At Broadband RF Frequencies
By Technical Paper Link - 25 Sep, 2024 - Comments: 0

A new technical paper titled "Characterizing the Broadband RF Permittivity of 3D-Integrated Layers in a Glass Wafer Stack from 100 MHz to 30 GHz" was published by researchers at NIST. Abstract "We present a method for accurately determining the permittivity of dielectric materials in 3D integrated structures at broadband RF frequencies. With applications of microwave and millimeter-wave ele... » read more

Formal Verification Of A Mixed Signal IP with Both Digital And Analog Blocks
By Technical Paper Link - 25 Sep, 2024 - Comments: 0

A new technical paper titled "Analogous Alignments: Digital "Formally" meets Analog" was published by researchers at Infineon Technologies. Abstract: "The complexity of modern-day System-on-Chips (SoCs) is continually increasing, and it becomes increasingly challenging to deliver dependable and credible chips in a short time-to-market. Especially, in the case of test chips, where the aim is... » read more

Maximizing Coverage Metrics with Formal Unreachability Analysis
By Synopsys - 25 Sep, 2024 - Comments: 0

Coverage lies at the very heart of functional verification. Whether designing a single intellectual property (IP) block or a huge system on chip (SoC), verification teams need to know how well the design has been tested. Functional coverage, code coverage, toggle coverage, assertion coverage, and other metrics are widely used. Improving tests to fill in coverage holes is a key part of the proce... » read more

Devising Security Solutions For Hardware Threats
By Adam Kovac - 25 Sep, 2024 - Comments: 0

Experts At The Table: Hardware security has evolved considerably in recent years, but getting products to market is a challenge in an environment where threats are always evolving and rarely predictable. That’s especially true given the sheer volume and variety of products being introduced. Semiconductor Engineering sat down with a panel of experts at the Design Automation Conference in San F... » read more

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