New Interconnect Metals Need New Dielectrics
By Katherine Derbyshire - 23 Jul, 2024 - Comments: 0

Just as circuit metallization must evolve to manage resistance as features shrink, so must the dielectric half of the interconnect stack. For quite some time, manufacturers have needed a dielectric constant (k) less than 4, which is the value for SiO2, but they have struggled to find materials that combine a low dielectric constant with mechanical and chemical stability. In work presented at... » read more

Multi-tier Die Stacking Through Collective Die-to-Wafer Hybrid bonding
By Brewer Science - 23 Jul, 2024 - Comments: 0

A technical paper titled "Multi-tier Die Stacking Through Collective Die-to-Wafer Hybrid bonding" was published by researchers at imec, Brewer Science and SUSS MicroTec Lithography GmbH. Abstract "A collective die-to-wafer bonding flow is extended beyond the N=2 tier to the N=3 and N=4 tier by collectively bonding multiple layers of dies on top of a target wafer. The N=2 die-level is show... » read more

Building A Sustainable And Diverse Semiconductor Workforce: Insights From ASMC 2024 Panel Discussion
By Krish Raghunath - 23 Jul, 2024 - Comments: 0

As the semiconductor industry works to attract talent to overcome its labor shortage, governments, educators, and the private sector must collaborate to make industry career opportunities more accessible for prospective employees. This concept provided the framework for a panel discussion during SEMI’s 35th annual Advanced Semiconductor Manufacturing Conference (ASMC) that took place in Alba... » read more

Survey of CXL Implementations and Standards (Intel, Microsoft)
By Technical Paper Link - 22 Jul, 2024 - Comments: 0

A new technical paper titled "An Introduction to the Compute Express Link (CXL) Interconnect" was published by researchers at Intel Corporation, Microsoft, and University of Washington. Abstract "The Compute Express Link (CXL) is an open industry-standard interconnect between processors and devices such as accelerators, memory buffers, smart network interfaces, persistent memory, and solid-... » read more

Improving Performance and Power Efficiency By Safely Eliminating Load Instruction Execution (ETH Zürich, Intel)
By Technical Paper Link - 22 Jul, 2024 - Comments: 0

A technical paper titled “Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution” was published by researchers at ETH Zürich and Intel Corporation.  This paper earned the Best Paper Award in the International Symposium on Computer Architecture (ISCA). Abstract: "Load instructions often limit instruction-level parallelism (ILP) in modern pr... » read more

ConvNext Runs 28X Faster Than Fallback
By Steve Roddy - 22 Jul, 2024 - Comments: 0

Two months ago in our blog we highlighted the fallacy of using a conventional NPU accelerator paired with a DSP or CPU for “fallback” operations. (Fallback Fails Spectacularly, May 2024). In that blog we calculated what the expected performance would be for a system with a DSP needing to perform the new operations found in one of today’s leading new ML networks – ConvNext. The result wa... » read more

Research Bits: July 22
By Jesse Allen - 22 Jul, 2024 - Comments: 0

Sub-1nm gate Researchers from Korea's Institute for Basic Science, Sungkyunkwan University, Harvard University, and Korea Advanced Institute of Science and Technology (KAIST) found a method that enables epitaxial growth of 1D metallic materials with a width of less than 1 nm, which they used as a gate electrode of a miniaturized transistor. The team controlled the crystal structure of molyb... » read more

Chip Industry Technical Paper Roundup: July 22
By Linda Christensen - 22 Jul, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library. [table id=245 /] More ReadingTechnical Paper Library home » read more

Chip Industry Week In Review
By The SE Staff - 19 Jul, 2024 - Comments: 0

The University of Texas at Austin’s Texas Institute for Electronics (TIE) was awarded $840 million to establish a Department of Defense microelectronics manufacturing center. This center will focus on developing advanced semiconductor microsystems to enhance U.S. defense systems. The project is part of DARPA's NGMM Program. The U.S. Dept. of Commerce announced preliminary terms with Global... » read more

Heat-Related Issues Impact Reliability In Advanced IC Designs
By Ann Mutschler - 18 Jul, 2024 - Comments: 1

Heat is becoming a much bigger problem in advanced-node chips and packages, causing critical electrons to leak out of DRAM, timing and reliability issues in 3D-ICs, and accelerated aging that are unique to different workloads. All types of circuitry are vulnerable to thermal effects. It can slow the movement of the electrons through wires, cause electromigration that shortens the lifespan of... » read more

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