Power Leadership At 2nm: Foundation IP Optimized For Next-Gen Hyperscale SoCs


By Andrew Appleby and Daryl Seitzer As demand for data center compute accelerates, power efficiency has become the defining metric for modern CPUs, GPUs, and AI accelerators. Every watt saved directly impacts the massive operating costs of gigawatt-scale AI data centers, where power and cooling account for 40–60% of operational expenditures. To reduce energy consumption and strengthen t... » read more

Scaling llama.cpp On Neoverse N2: Solving Cross-NUMA Performance Issues


This blog post explains the cross-NUMA memory access issue that occurs when you run llama.cpp in Neoverse. It also introduces a proof-of-concept patch that addresses this issue and can provide up to a 55% performance increase for text generation when you run the llama3_Q4_0 model on the ZhuFeng Neoverse system. Cross-NUMA memory access problem In llama.cpp, performance drops when the number o... » read more

Minimum Energy Per Query


Key Takeaways Extracting heat from a chip faster is a short-term fix to a bigger problem. The longer-term challenge is how to reduce the amount of energy used per query. Data movement, guardbanding, and software inefficiency are key targets for the future. Heat is a serious problem within AI chips, and it is limiting how much processing can be done. The solution is either to... » read more

Autonomous Driving: Assessment Of YOLO Algorithms (RMIT et al.)


A new technical paper titled "Advances in You Only Look Once (YOLO) algorithms for lane and object detection in autonomous vehicles" was published by RMIT University, Kyungpook National University, Deakin University and the RCA Robotics Laboratory, Royal College of Art. Abstract "Ensuring the safety and efficiency of Autonomous Vehicles (AVs) necessitates highly accurate perception, especia... » read more

Neuromorphic HW That Detects Motion Changes 4X Faster (Beihang, BIT, KAUST, Cambridge et al.)


A new technical paper titled "Ultrafast visual perception beyond human capabilities enabled by motion analysis using synaptic transistors" was published by researchers at Beihang University, Beijing Institute of Technology, KAUST, University of Cambridge and others. Excerpt from Abstract "We introduce a neuromorphic temporal-attention hardware that emulates the interaction between the ret... » read more

Simulate Faster with SimAI Software for High Returns at a Low Cost of Ownership


While the value of engineering simulation has been proven for decades, only a small percentage of engineers report using artificial intelligence (AI) to amplify their simulation results at scale. However, AI has the potential to make large-scale simulations even faster, more precise, and more cost-effective. AI-enabled simulation not only amplifies the performance and returns of simulatio... » read more

Future-Proofing System Design


This whitepaper has explored how converging forces—AI-driven workloads, heterogeneous integration, and increasingly complex security requirements—are transforming design priorities. Adaptability, openness, and lifecycle management are no longer secondary considerations but core architectural imperatives. Standardization through initiatives such as UCIe and OCP fosters interoperability and s... » read more

5 Strategic Decisions for Building a Scalable Compute Platform for Now and the Future


Artificial intelligence (AI) is no longer a “nice-to-have” technology—it’s a central driver of competitive advantage and business innovation. Across industries, enterprises are moving beyond experimentation and embedding AI into all their products, workflows, and customer experiences. But as organizations scale, many are discovering a stark reality: their compute infrastructure was not ... » read more

Optimal Surface Condition For Improved Cu-to-Cu Direct Bonding (NCHU, Osaka Univ.)


A new technical paper titled "Hybrid surface pre-treatments for enhancing copper-to-copper direct bonding" was published by researchers at National Chung Hsing University (NCHU) and Osaka University. Abstract excerpt "Three-dimensional integrated circuits (3D IC) require low-temperature, high-reliability Cu–Cu direct bonding to support fine-pitch vertical interconnects and heterogeneous... » read more

Information Flow Verification Framework Integrating Static and Formal Verification Methods At The Pre-Silicon Stage (U. of Florida)


Researchers from University of Florida published "IFV: Information Flow Verification at the Pre-silicon Stage Utilizing Static-Formal Methodology." Abstract "Modern system-on-chips (SoCs) are becoming prone to numerous security vulnerabilities due to their ever-growing complexity and size. Therefore, a comprehensive security verification framework is needed at the very early stage of the ... » read more

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